Has the U.S. Tech Sector valuation changed over the past few years?

Investors are pessimistic on the American Information Technology industry, indicating that they anticipate long term growth rates will be lower than they have historically. The industry is trading at a PE ratio of 41.2x which is lower than its 3-year average PE of 45.3x. The 3-year average PS ratio of 7.6x is lower than the industry's current PS ratio of 9.2x.

Which industries have driven the changes within the U.S. Tech sector?

Investors are most optimistic about the Electronic Equipment and Components industry which is trading above its 3-year average PE ratio of 34.2x. Analysts are expecting annual earnings growth of 27.1%, which is higher than its past year's earnings growth of 10.1% per year. Investors are most pessimistic about the Software industry, which is trading below its 3-year average of 50.8x.

U.S. Tech Sector Analysis

Date	Market Cap	Revenue	Earnings	PE	Absolute PE	PS
Fri, 26 Jun 2026	US$26.6t	US$2.9t	US$644.9b	32.1x	41.2x	9.2x
Sun, 24 May 2026	US$21.6t	US$2.8t	US$611.2b	35.1x	35.4x	7.7x
Tue, 21 Apr 2026	US$23.7t	US$2.7t	US$550.6b	33.4x	43x	8.8x
Thu, 19 Mar 2026	US$21.4t	US$2.7t	US$543.3b	30.4x	39.3x	8x
Sat, 14 Feb 2026	US$21.4t	US$2.6t	US$520.7b	30.4x	41x	8.1x
Mon, 12 Jan 2026	US$22.6t	US$2.6t	US$507.0b	32.4x	44.5x	8.7x
Wed, 10 Dec 2025	US$23.2t	US$2.6t	US$495.7b	31.2x	46.9x	9x
Fri, 07 Nov 2025	US$23.4t	US$2.5t	US$477.9b	30.4x	48.9x	9.2x
Sun, 05 Oct 2025	US$22.7t	US$2.5t	US$439.2b	31.7x	51.8x	9.1x
Tue, 02 Sep 2025	US$20.8t	US$2.5t	US$429.3b	29.4x	48.5x	8.5x
Thu, 31 Jul 2025	US$20.7t	US$2.4t	US$393.3b	27.7x	52.7x	8.7x
Sat, 28 Jun 2025	US$19.6t	US$2.4t	US$393.2b	28.4x	49.8x	8.2x
Mon, 26 May 2025	US$17.5t	US$2.4t	US$385.8b	26.9x	45.5x	7.4x
Wed, 23 Apr 2025	US$14.5t	US$2.3t	US$386.6b	24.6x	37.4x	6.2x
Fri, 21 Mar 2025	US$16.6t	US$2.3t	US$386.1b	27.3x	42.9x	7.1x
Sun, 16 Feb 2025	US$18.9t	US$2.3t	US$369.9b	32.4x	51x	8.2x
Tue, 14 Jan 2025	US$18.0t	US$2.3t	US$367.2b	32.3x	49x	8x
Thu, 12 Dec 2024	US$18.5t	US$2.3t	US$362.8b	33.1x	50.9x	8.2x
Sat, 09 Nov 2024	US$18.3t	US$2.2t	US$352.5b	33.3x	52x	8.2x
Mon, 07 Oct 2024	US$17.2t	US$2.2t	US$378.1b	29.7x	45.4x	7.9x
Wed, 04 Sep 2024	US$16.8t	US$2.2t	US$378.3b	28.7x	44.4x	7.8x
Fri, 02 Aug 2024	US$16.5t	US$2.1t	US$365.6b	30.7x	45.2x	7.8x
Sun, 30 Jun 2024	US$16.8t	US$2.1t	US$362.8b	29.7x	46.4x	8x
Tue, 28 May 2024	US$15.4t	US$2.1t	US$349.9b	30.3x	43.9x	7.5x
Thu, 25 Apr 2024	US$13.9t	US$2.0t	US$327.8b	28.4x	42.5x	6.8x
Sat, 23 Mar 2024	US$14.9t	US$2.0t	US$328.6b	27.8x	45.4x	7.3x
Mon, 19 Feb 2024	US$14.2t	US$2.0t	US$310.2b	27.5x	45.9x	7x
Wed, 17 Jan 2024	US$13.4t	US$2.0t	US$292.0b	25.7x	46x	6.5x
Fri, 15 Dec 2023	US$13.2t	US$2.1t	US$293.6b	26.2x	45x	6.4x
Sun, 12 Nov 2023	US$12.3t	US$2.0t	US$279.7b	23.4x	44.1x	6.1x
Tue, 10 Oct 2023	US$11.8t	US$2.0t	US$269.8b	24.7x	43.8x	5.8x
Thu, 07 Sep 2023	US$12.1t	US$2.0t	US$272.7b	24.1x	44.5x	5.9x
Sat, 05 Aug 2023	US$11.9t	US$2.0t	US$262.2b	25.6x	45.4x	5.9x
Mon, 03 Jul 2023	US$12.0t	US$2.0t	US$259.9b	25x	46.3x	5.9x


US Market	-2.68%
Tech	-5.04%
Electronic Equipment and Components	2.94%
Communications	-0.49%
IT	-1.55%
Semiconductors	-4.58%
Tech Hardware	-6.73%
Software	-7.03%

Company	Last Price	7D	1Y	Valuation
MU Micron Technology	US$1.21k	7.0% +US$89.7b	863.1%	PE27.1x
AMAT Applied Materials	US$668.00	8.2% +US$40.4b	264.6%	PE62.3x
GLW Corning	US$228.01	17.0% +US$28.5b	341.0%	PE108.4x
SNDK Sandisk	US$2.34k	6.9% +US$22.3b	4,822.0%	PE76.7x
LRCX Lam Research	US$401.82	3.3% +US$16.0b	314.9%	PE74.9x

Announcement • 3h

IBM Unveils World's First Sub-1 Nanometer Chip Technology Featuring Nanostack 3D Architecture

IBM unveiled a major semiconductor breakthrough with the introduction of the world's first sub-1 nanometer (nm) chip technology, featuring a revolutionary transistor architecture at the 0.7 nm, or 7 angstrom node. IBM's new sub-1 nm chip packs nearly 100 billion transistors onto a chip the size of a fingernail, nearly twice the density of IBM's 2 nm chip, unveiled in 2021. Enabled by a series of structural and material innovations, including IBM's groundbreaking three-dimensional nanostack architecture, the technology demonstrates how continued gains in performance and efficiency remain possible even as chip features approach atomic dimensions. Published technical results report the new chip is projected to offer a substantial leap in capability—up to 50% more performance, or 70% greater energy efficiency than IBM's 2 nm node chips—supercharging compute for applications ranging from generative AI and cloud infrastructure to next-generation electronic devices. To produce this chip, IBM researchers developed an entirely new transistor architecture, called 'nanostack,' the industry's first known three-dimensional, nanosheet-based design. Nanostack represents a major advance beyond nanosheet technology, the industry's current leading-edge architecture, invented by IBM. The nanostack design vertically stacks and staggers transistors, taking advantage of 3D sequential integration to pack more transistors onto a chip. The design also unlocks the use of different material combinations within each stacked layer, optimizing performance and power efficiency of each transistor independent of the other. IBM's nanostack architecture was experimentally validated through ultra-thin dielectric bonding in CMOS integration, demonstration of dual-channel engineering capability, and functional CMOS inverter operation with expected switching performance. Together, these results confirm the nanostack technology can be physically built and supports real computation. In new research presented at VLSI 2026, IBM researchers demonstrated that the nanostack architecture provides 40% scaling in SRAM, unlocking the ability of chip designers to create much more efficient chips while also supporting the high-bandwidth data demands of advanced AI workloads. With this groundbreaking structure, logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM's 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible. With the new nanostack architecture, IBM's semiconductor roadmap projects at least a decade of future scaling. IBM and its partners conduct this work at a semiconductor research facility in Albany, New York, which will soon be home to a High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography tool, essential for the future of logic scaling. Developed by ASML, this technology enables ultra-precise circuit printing, supporting the creation of smaller, more powerful chips. IBM and partners including Lam Research Corp., Tokyo Electron (TEL), and SCREEN Semiconductor Solutions Ltd. have been working together to develop new High NA EUV processes and tools that have already yielded working devices. IBM also recently announced a plan to form Anderon, the world's first pure-play quantum foundry. Anderon, a standalone IBM company, will draw on IBM's quantum computing and semiconductor expertise to help position the United States to manufacture most of the world's quantum wafers. With the expectation of the earliest adoption of nanostack technology at the sub-1 nm node, IBM sees a path to production in as early as the next 5 years.

Announcement • 3h

Applied Materials, Inc. Introduces New Chipmaking Systems for 3D Architectures in AI Chips

Applied Materials, Inc. introduced a suite of new chipmaking systems for building the advanced 3D chip architectures that power next-generation AI. A new epitaxy system optimized for DRAM fabs adds a critical logic-class step—boosting memory speed and efficiency while maximizing output within tight fab footprint and supply constraints. New CMP and deposition systems target the most critical advanced packaging steps, delivering higher-yield chip stacking for HBM and logic. New eBeam systems bring wafer-fab-grade metrology and defect review to advanced packaging, optimized to handle the unique challenges these packages present. Epitaxy has been used for years in leading-edge logic, where precision growth of a crystalline material in the transistor channel has boosted performance well beyond what geometric scaling alone can deliver. Those same techniques are now becoming critical in DRAM peripheral transistors. Applied pioneered silicon germanium epitaxy in transistor channels more than a decade ago with its Centura Prime Epi system. Applied is now introducing an enhanced Centura Prime Epi system that selectively grows doped silicon germanium and silicon phosphorous in source/drain regions, combining advanced strain engineering with precise doping control. The result is higher drive current and transistor efficiency, enabling faster, more power-efficient DRAM operation—essential for the bandwidth demands of HBM and next-generation DDR. The new system also features a 20% smaller footprint, enabling higher tool density and faster capacity scaling in DRAM fabs. In recent years, advanced packaging has become as strategically important to the computing industry as on-chip transistor scaling. Modern AI server chips pack trillions of transistors by integrating multiple dies into a single package. HBM is a leading example of this approach, stacking DRAM chips on top of one another and connecting them with through-silicon vias (TSVs). Applied is the leader in process equipment for advanced packaging, including systems covering the majority of materials engineering steps required to create the TSVs, copper pillars and microbumps that connect stacked dies. Applied is introducing three new systems targeting the most critical advanced packaging process steps. Leveraging Applied’s leadership position in chemical mechanical planarization (CMP), the Opta Quad platform is engineered specifically for advanced packaging, where thicker films, longer polish times and tighter tolerances raise the risk of non-uniformity and yield loss. Opta Quad continuously monitors wafer conditions during polish and dynamically adjusts in real time, improving within-wafer uniformity and total thickness variation control. This is particularly critical for hybrid bonding—an emerging 3D stacking technology in which copper wiring and surrounding dielectrics from two chips are fused together in a single step, requiring near-perfect surface planarity for high-yield results. Nokota VMax 2 is an electrochemical deposition (ECD) system engineered for high-precision copper plating across a broad range of applications for next-generation packaging, from TSV fill for 3D stacking to fine-pitch interconnects such as microbump formation. Nokota VMax 2 introduces Adaptive Pattern Tuning (APT), which dynamically shapes the electric field to correct for layout-driven variation and improve plating uniformity across the wafer. Producer Avila 2 is a plasma-enhanced chemical vapor deposition (PECVD) system that improves the mechanical stability of ultra-thin DRAM dies by depositing stress-balanced dielectric films around TSVs, enabling reliable stacking of 12, 16, and future high-layer-count HBM designs. In addition to HBM, the system supports a range of advanced memory and logic integration schemes. Advanced packaging fabs are encountering defect and metrology challenges once exclusively found in wafer fabs. Feature dimensions have shrunk below the resolution limit of optical inspection tools, and particles that were tolerable with larger bumps now impact yield. A single defect can require scrapping an entire HBM stack, elevating process control to a strategic priority. Applied is extending its eBeam leadership with two new systems specifically designed for advanced packaging—both engineered to handle a wide range of substrate geometries and materials. The latest in Applied’s VeritySEM portfolio for critical dimension (CD) metrology, VeritySEM 7AP enables precise measurement of features on thick, heterogeneous, and highly warped substrates common in HBM and chiplet architectures. VeritySEM AP systems automatically reconfigure to support a range of sizes and materials, while delivering sub-10nm sensitivity—orders of magnitude better than optical tools. SEMVision is the industry’s leading eBeam defect analysis platform. SEMVision G7AP extends Applied’s leadership into advanced packaging, enabling high-resolution defect review and automated classification across silicon, organic, and glass substrates. The system can accelerate yield learning by helping customers quickly distinguish critical defects from nuisance signals. SEMVision G7AP is already in production at memory and logic manufacturers supporting high-volume advanced packaging. A media kit with additional information on the new systems is available.

U.S. Tech Sector Analysis

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IBM Unveils World's First Sub-1 Nanometer Chip Technology Featuring Nanostack 3D Architecture

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