View Financial HealthSocionext 배당 및 자사주 매입배당 기준 점검 1/6Socionext 은(는) 현재 수익률이 1.73% 인 배당금 지급 회사입니다.핵심 정보1.7%배당 수익률1.0%자사주 매입 수익률총 주주 수익률2.7%미래 배당 수익률1.8%배당 성장률n/a다음 배당 지급일n/a배당락일n/a주당 배당금n/a배당 성향101%최근 배당 및 자사주 매입 업데이트업데이트 없음모든 업데이트 보기Recent updates공시 • Apr 29Socionext Inc., Annual General Meeting, Jun 25, 2026Socionext Inc., Annual General Meeting, Jun 25, 2026.공시 • Mar 10Socionext Inc. to Report Fiscal Year 2026 Results on Apr 28, 2026Socionext Inc. announced that they will report fiscal year 2026 results on Apr 28, 2026공시 • Dec 12Socionext Inc. to Report Q3, 2026 Results on Jan 30, 2026Socionext Inc. announced that they will report Q3, 2026 results on Jan 30, 2026공시 • Oct 28Socionext Unveils Flexlets, A Configurable Chiplet Ecosystem to Accelerate Multi-Die Silicon InnovationSocionext Inc. introduced "Flexlets", a new class of configurable chiplets designed to advance heterogenous integration. As traditional monolithic SoC designs face physical and economic limits--reticle size constraints, yield challenges, and thermal bottlenecks- the industry is turning toward chiplet-based design, where designers can integrate their core features and interface functionalities, provided as chiplets, into a packaged device to improve performance, cost, and accelerate time-to-market. While chiplet technology opens exciting possibilities for modular designs and scalability, many current solutions are derived from fixed-function ASSPs, limiting flexibility and customization. Socionext's Flexlets overcome this by offering a configurable library of chiplet designs at the RTL level. Customers have the option to customize their designs at the RTL level to meet specific application requirements. Engineering samples of the initial Flexlet base designs, including Known Good Die (KGD), are currently in development. Socionext will initiate its first customer design this year and broaden design engagements beginning in Second Quarter calendar year 2026. Memory Expansion Flexlets: Scalable memory solutions with support for the latest DDR/LPDDR standards connected to either UCIe-S or UALink; Ethernet Controller Flexlets: Robust and high-performance networking connectivity via 224G/UE bridged to UCIe 2.0; PCIe Controller Flexlets: Seamless integration to PCIe ecosystem by bridging PCIe Gen7 128G PHY to UCIe 2. 0 with configurable lanes; Hybrid PCIe + Ethernet Controller Flexlets: A versatile range of I/O capabilities, bridging high-speed SerDes (224G/UE) to UCIe 2.2.0. All Flexlets support 2.5D/3D advanced packaging, including CoWoS, SoW-X, EMIB, and 3D stacking, process nodes (5, 3, 2nm), and industry standards, including UCIe, UALink, PCIe Gen7, and Ultra Ethernet - enabling robust interoperability across multi-vendor ecosystems. Socionext's packaging capabilities rival those of the largest chipmakers. With successful tapeouts in 2nm and 3DIC test vehicles, company offer real-world proof of engineering excellence, including support of multiple - 64 to 128 - instances of high-speed 224G SerDes in a Flexlet. In a market still lacking standardized design rule checks for large chiplet-based packages, Socionext provides the credibility and capability customers need to innovate with confidence.공시 • Sep 12Socionext Inc. to Report Q2, 2026 Results on Oct 31, 2025Socionext Inc. announced that they will report Q2, 2026 results on Oct 31, 2025공시 • Aug 28Socionext Expands 3DIC Support with Advanced 3D Die Stacking and 5.5D in Packaging PortfolioSocionext announced the availability of 3DIC support in its portfolio of well-proven capabilities for the delivery of complete solutions for consumer, AI, and HPC data center applications that include chiplets, 2.5D, 3D, and 5.5D packaging. Socionext empowers customers with a proven development process and unmatched expertise delivering high-performance, high-quality solutions that accelerate innovation and success. As a key milestone, Socionext has successfully taped out a complete packaged device leveraging TSMC's SoIC-X 3D stacking. The design combines an N3 compute die and an N5 I/O die in a face-to-face (F2F) configuration. The F2F 3D stacking approach minimizes interconnect distance, significantly reduces signal latency and power consumption compared to traditional 2D and 2.5D designs. Building on the company's experience in 2.5D designs, Socionext applies proven design experience and methodologies to 3DICs, which stack components vertically to unlock key advantages: View the 3DIC F2F and 5.5D Structure; Heterogeneous Integration: 3D ICs enable the integration of different technology nodes (3nm, 5nm, 7nm) and functions (e.g., logic, memory, interface) into a single package, allowing for a more optimally partitioned solution addressing performance, density, and cost; Higher Integration Density for a Broader Range of Applications; vertical stacking enables greater functionality in a smaller footprint--an essential advantage as traditional scaling nears its limits. This is especially valuable for space-constrained consumer devices; Improved Performance; Shorter, wider connections between dies reduce latency and boost bandwidth; Lower Power consumption; Compact interconnects result in reduced drive requirements due to lower impedance. A Vision for the Future: The introduction of 3DIC, along with 5.5D support, reflects Socionext's strong focus on advancing heterogeneous integration, bringing together multiple functions within a unified system of semiconductors and packaging elements. As demand grows for scalable, high-density, and energy-efficient platforms, especially in consumer, AI, and data center applications, 3DICs will play a pivotal role in shaping the future of semiconductor innovation.공시 • Jun 11Socionext Inc. to Report Q1, 2026 Results on Jul 31, 2025Socionext Inc. announced that they will report Q1, 2026 results on Jul 31, 2025공시 • Apr 28+ 1 more updateSocionext Inc., Annual General Meeting, Jun 26, 2025Socionext Inc., Annual General Meeting, Jun 26, 2025.공시 • Mar 11Socionext Inc. to Report Fiscal Year 2025 Results on Apr 28, 2025Socionext Inc. announced that they will report fiscal year 2025 results on Apr 28, 2025지급의 안정성과 성장배당 데이터 가져오는 중안정적인 배당: 배당금 지급이 안정적인 반면, SOCN.F 은(는) 배당금을 지급한 지 10년도 채 되지 않았습니다.배당금 증가: SOCN.F 의 배당금 지급이 증가했지만 회사는 3 년 동안만 배당금을 지급했습니다.배당 수익률 vs 시장Socionext 배당 수익률 vs 시장SOCN.F의 배당 수익률은 시장과 어떻게 비교되나요?구분배당 수익률회사 (SOCN.F)1.7%시장 하위 25% (US)1.4%시장 상위 25% (US)4.2%업계 평균 (Semiconductor)0.5%분석가 예측 (SOCN.F) (최대 3년)1.8%주목할만한 배당금: SOCN.F 의 배당금( 1.73% )은 US 시장에서 배당금 지급자의 하위 25%( 1.41% )보다 높습니다.고배당: SOCN.F 의 배당금( 1.73% )은 US 시장에서 배당금 지급자의 상위 25%( 4.22% )와 비교해 낮습니다.주주 대상 이익 배당수익 보장: 지급 비율 ( 100.5% )이 높기 때문에 SOCN.F 의 배당금 지급은 수익으로 잘 충당되지 않습니다.주주 현금 배당현금 흐름 범위: SOCN.F 배당금을 지급하고 있지만 회사에는 잉여현금흐름이 없습니다.높은 배당을 제공하는 우량 기업 찾기7D1Y7D1Y7D1YUS 시장에서 배당이 강한 기업.View Management기업 분석 및 재무 데이터 상태데이터최종 업데이트 (UTC 시간)기업 분석2026/05/26 20:42종가2026/05/22 00:00수익2026/03/31연간 수익2026/03/31데이터 소스당사의 기업 분석에 사용되는 데이터는 S&P Global Market Intelligence LLC에서 제공됩니다. 아래 데이터는 이 보고서를 생성하기 위해 분석 모델에서 사용됩니다. 데이터는 정규화되므로 소스가 제공된 후 지연이 발생할 수 있습니다.패키지데이터기간미국 소스 예시 *기업 재무제표10년손익계산서현금흐름표대차대조표SEC 양식 10-KSEC 양식 10-Q분석가 컨센서스 추정치+3년재무 예측분석가 목표주가분석가 리서치 보고서Blue Matrix시장 가격30년주가배당, 분할 및 기타 조치ICE 시장 데이터SEC 양식 S-1지분 구조10년주요 주주내부자 거래SEC 양식 4SEC 양식 13D경영진10년리더십 팀이사회SEC 양식 10-KSEC 양식 DEF 14A주요 개발10년회사 공시SEC 양식 8-K* 미국 증권에 대한 예시이며, 비(非)미국 증권에는 해당 국가의 규제 서식 및 자료원을 사용합니다.별도로 명시되지 않는 한 모든 재무 데이터는 연간 기간을 기준으로 하지만 분기별로 업데이트됩니다. 이를 TTM(최근 12개월) 또는 LTM(지난 12개월) 데이터라고 합니다. 자세히 알아보기.분석 모델 및 스노우플레이크이 보고서를 생성하는 데 사용된 분석 모델에 대한 자세한 내용은 당사의 Github 페이지에서 확인하실 수 있습니다. 또한 보고서 활용 방법에 대한 가이드와 YouTube 튜토리얼도 제공합니다.Simply Wall St 분석 모델을 설계하고 구축한 세계적 수준의 팀에 대해 알아보세요.산업 및 섹터 지표산업 및 섹터 지표는 Simply Wall St가 6시간마다 계산하며, 프로세스에 대한 자세한 내용은 Github에서 확인할 수 있습니다.분석가 소스Socionext Inc.는 5명의 분석가가 다루고 있습니다. 이 중 5명의 분석가가 우리 보고서에 입력 데이터로 사용되는 매출 또는 수익 추정치를 제출했습니다. 분석가의 제출 자료는 하루 종일 업데이트됩니다.분석가기관Takero FujiwaraCitigroup IncHiroshi TaguchiMacquarie ResearchKazuo YoshikawaMorgan Stanley2명의 분석가 더 보기
공시 • Apr 29Socionext Inc., Annual General Meeting, Jun 25, 2026Socionext Inc., Annual General Meeting, Jun 25, 2026.
공시 • Mar 10Socionext Inc. to Report Fiscal Year 2026 Results on Apr 28, 2026Socionext Inc. announced that they will report fiscal year 2026 results on Apr 28, 2026
공시 • Dec 12Socionext Inc. to Report Q3, 2026 Results on Jan 30, 2026Socionext Inc. announced that they will report Q3, 2026 results on Jan 30, 2026
공시 • Oct 28Socionext Unveils Flexlets, A Configurable Chiplet Ecosystem to Accelerate Multi-Die Silicon InnovationSocionext Inc. introduced "Flexlets", a new class of configurable chiplets designed to advance heterogenous integration. As traditional monolithic SoC designs face physical and economic limits--reticle size constraints, yield challenges, and thermal bottlenecks- the industry is turning toward chiplet-based design, where designers can integrate their core features and interface functionalities, provided as chiplets, into a packaged device to improve performance, cost, and accelerate time-to-market. While chiplet technology opens exciting possibilities for modular designs and scalability, many current solutions are derived from fixed-function ASSPs, limiting flexibility and customization. Socionext's Flexlets overcome this by offering a configurable library of chiplet designs at the RTL level. Customers have the option to customize their designs at the RTL level to meet specific application requirements. Engineering samples of the initial Flexlet base designs, including Known Good Die (KGD), are currently in development. Socionext will initiate its first customer design this year and broaden design engagements beginning in Second Quarter calendar year 2026. Memory Expansion Flexlets: Scalable memory solutions with support for the latest DDR/LPDDR standards connected to either UCIe-S or UALink; Ethernet Controller Flexlets: Robust and high-performance networking connectivity via 224G/UE bridged to UCIe 2.0; PCIe Controller Flexlets: Seamless integration to PCIe ecosystem by bridging PCIe Gen7 128G PHY to UCIe 2. 0 with configurable lanes; Hybrid PCIe + Ethernet Controller Flexlets: A versatile range of I/O capabilities, bridging high-speed SerDes (224G/UE) to UCIe 2.2.0. All Flexlets support 2.5D/3D advanced packaging, including CoWoS, SoW-X, EMIB, and 3D stacking, process nodes (5, 3, 2nm), and industry standards, including UCIe, UALink, PCIe Gen7, and Ultra Ethernet - enabling robust interoperability across multi-vendor ecosystems. Socionext's packaging capabilities rival those of the largest chipmakers. With successful tapeouts in 2nm and 3DIC test vehicles, company offer real-world proof of engineering excellence, including support of multiple - 64 to 128 - instances of high-speed 224G SerDes in a Flexlet. In a market still lacking standardized design rule checks for large chiplet-based packages, Socionext provides the credibility and capability customers need to innovate with confidence.
공시 • Sep 12Socionext Inc. to Report Q2, 2026 Results on Oct 31, 2025Socionext Inc. announced that they will report Q2, 2026 results on Oct 31, 2025
공시 • Aug 28Socionext Expands 3DIC Support with Advanced 3D Die Stacking and 5.5D in Packaging PortfolioSocionext announced the availability of 3DIC support in its portfolio of well-proven capabilities for the delivery of complete solutions for consumer, AI, and HPC data center applications that include chiplets, 2.5D, 3D, and 5.5D packaging. Socionext empowers customers with a proven development process and unmatched expertise delivering high-performance, high-quality solutions that accelerate innovation and success. As a key milestone, Socionext has successfully taped out a complete packaged device leveraging TSMC's SoIC-X 3D stacking. The design combines an N3 compute die and an N5 I/O die in a face-to-face (F2F) configuration. The F2F 3D stacking approach minimizes interconnect distance, significantly reduces signal latency and power consumption compared to traditional 2D and 2.5D designs. Building on the company's experience in 2.5D designs, Socionext applies proven design experience and methodologies to 3DICs, which stack components vertically to unlock key advantages: View the 3DIC F2F and 5.5D Structure; Heterogeneous Integration: 3D ICs enable the integration of different technology nodes (3nm, 5nm, 7nm) and functions (e.g., logic, memory, interface) into a single package, allowing for a more optimally partitioned solution addressing performance, density, and cost; Higher Integration Density for a Broader Range of Applications; vertical stacking enables greater functionality in a smaller footprint--an essential advantage as traditional scaling nears its limits. This is especially valuable for space-constrained consumer devices; Improved Performance; Shorter, wider connections between dies reduce latency and boost bandwidth; Lower Power consumption; Compact interconnects result in reduced drive requirements due to lower impedance. A Vision for the Future: The introduction of 3DIC, along with 5.5D support, reflects Socionext's strong focus on advancing heterogeneous integration, bringing together multiple functions within a unified system of semiconductors and packaging elements. As demand grows for scalable, high-density, and energy-efficient platforms, especially in consumer, AI, and data center applications, 3DICs will play a pivotal role in shaping the future of semiconductor innovation.
공시 • Jun 11Socionext Inc. to Report Q1, 2026 Results on Jul 31, 2025Socionext Inc. announced that they will report Q1, 2026 results on Jul 31, 2025
공시 • Apr 28+ 1 more updateSocionext Inc., Annual General Meeting, Jun 26, 2025Socionext Inc., Annual General Meeting, Jun 26, 2025.
공시 • Mar 11Socionext Inc. to Report Fiscal Year 2025 Results on Apr 28, 2025Socionext Inc. announced that they will report fiscal year 2025 results on Apr 28, 2025