Socionext（SOCN.F）株式概要ソシオネクスト株式会社は、システム・オン・チップ（SoC）およびSoCを中心としたソリューション／サービスの設計、開発、製造、販売を世界中で行っています。 詳細SOCN.F ファンダメンタル分析スノーフレーク・スコア評価3/6将来の成長3/6過去の実績1/6財務の健全性6/6配当金1/6報酬当社が推定した公正価値より13.2%で取引されている 収益は年間28.98%増加すると予測されています リスク分析1.84%の配当は、利益やフリーキャッシュフローによって十分にカバーされていない 高いレベルの非現金収入 株式の流動性は非常に低い 利益率(4.3%)は昨年より低い(10.4%) すべてのリスクチェックを見るSOCN.F Community Fair Values Create NarrativeSee what others think this stock is worth. Follow their fair value or set your own to get alerts.Your Fair ValueUS$Current PriceUS$17.2910.8% 割高 内在価値ディスカウントGrowth estimate overAnnual revenue growth rate5 Yearstime period%/yrDecreaseIncreasePastFuture0325b2016201920222025202620282031Revenue JP¥325.4bEarnings JP¥14.1bAdvancedSet Fair ValueView all narrativesSocionext Inc. 競合他社Himax TechnologiesSymbol: NasdaqGS:HIMXMarket cap: US$3.5bPenguin SolutionsSymbol: NasdaqGS:PENGMarket cap: US$2.5bDiodesSymbol: NasdaqGS:DIODMarket cap: US$4.4bUniversal DisplaySymbol: NasdaqGS:OLEDMarket cap: US$4.3b価格と性能株価の高値、安値、推移の概要Socionext過去の株価現在の株価JP¥17.2952週高値JP¥20.8752週安値JP¥11.00ベータ0.541ヶ月の変化54.88%3ヶ月変化n/a1年変化n/a3年間の変化n/a5年間の変化n/aIPOからの変化-6.53%最新ニュースお知らせ • Apr 29Socionext Inc., Annual General Meeting, Jun 25, 2026Socionext Inc., Annual General Meeting, Jun 25, 2026.お知らせ • Mar 10Socionext Inc. to Report Fiscal Year 2026 Results on Apr 28, 2026Socionext Inc. announced that they will report fiscal year 2026 results on Apr 28, 2026お知らせ • Dec 12Socionext Inc. to Report Q3, 2026 Results on Jan 30, 2026Socionext Inc. announced that they will report Q3, 2026 results on Jan 30, 2026お知らせ • Oct 28Socionext Unveils Flexlets, A Configurable Chiplet Ecosystem to Accelerate Multi-Die Silicon InnovationSocionext Inc. introduced "Flexlets", a new class of configurable chiplets designed to advance heterogenous integration. As traditional monolithic SoC designs face physical and economic limits--reticle size constraints, yield challenges, and thermal bottlenecks- the industry is turning toward chiplet-based design, where designers can integrate their core features and interface functionalities, provided as chiplets, into a packaged device to improve performance, cost, and accelerate time-to-market. While chiplet technology opens exciting possibilities for modular designs and scalability, many current solutions are derived from fixed-function ASSPs, limiting flexibility and customization. Socionext's Flexlets overcome this by offering a configurable library of chiplet designs at the RTL level. Customers have the option to customize their designs at the RTL level to meet specific application requirements. Engineering samples of the initial Flexlet base designs, including Known Good Die (KGD), are currently in development. Socionext will initiate its first customer design this year and broaden design engagements beginning in Second Quarter calendar year 2026. Memory Expansion Flexlets: Scalable memory solutions with support for the latest DDR/LPDDR standards connected to either UCIe-S or UALink; Ethernet Controller Flexlets: Robust and high-performance networking connectivity via 224G/UE bridged to UCIe 2.0; PCIe Controller Flexlets: Seamless integration to PCIe ecosystem by bridging PCIe Gen7 128G PHY to UCIe 2. 0 with configurable lanes; Hybrid PCIe + Ethernet Controller Flexlets: A versatile range of I/O capabilities, bridging high-speed SerDes (224G/UE) to UCIe 2.2.0. All Flexlets support 2.5D/3D advanced packaging, including CoWoS, SoW-X, EMIB, and 3D stacking, process nodes (5, 3, 2nm), and industry standards, including UCIe, UALink, PCIe Gen7, and Ultra Ethernet - enabling robust interoperability across multi-vendor ecosystems. Socionext's packaging capabilities rival those of the largest chipmakers. With successful tapeouts in 2nm and 3DIC test vehicles, company offer real-world proof of engineering excellence, including support of multiple - 64 to 128 - instances of high-speed 224G SerDes in a Flexlet. In a market still lacking standardized design rule checks for large chiplet-based packages, Socionext provides the credibility and capability customers need to innovate with confidence.お知らせ • Sep 12Socionext Inc. to Report Q2, 2026 Results on Oct 31, 2025Socionext Inc. announced that they will report Q2, 2026 results on Oct 31, 2025お知らせ • Aug 28Socionext Expands 3DIC Support with Advanced 3D Die Stacking and 5.5D in Packaging PortfolioSocionext announced the availability of 3DIC support in its portfolio of well-proven capabilities for the delivery of complete solutions for consumer, AI, and HPC data center applications that include chiplets, 2.5D, 3D, and 5.5D packaging. Socionext empowers customers with a proven development process and unmatched expertise delivering high-performance, high-quality solutions that accelerate innovation and success. As a key milestone, Socionext has successfully taped out a complete packaged device leveraging TSMC's SoIC-X 3D stacking. The design combines an N3 compute die and an N5 I/O die in a face-to-face (F2F) configuration. The F2F 3D stacking approach minimizes interconnect distance, significantly reduces signal latency and power consumption compared to traditional 2D and 2.5D designs. Building on the company's experience in 2.5D designs, Socionext applies proven design experience and methodologies to 3DICs, which stack components vertically to unlock key advantages: View the 3DIC F2F and 5.5D Structure; Heterogeneous Integration: 3D ICs enable the integration of different technology nodes (3nm, 5nm, 7nm) and functions (e.g., logic, memory, interface) into a single package, allowing for a more optimally partitioned solution addressing performance, density, and cost; Higher Integration Density for a Broader Range of Applications; vertical stacking enables greater functionality in a smaller footprint--an essential advantage as traditional scaling nears its limits. This is especially valuable for space-constrained consumer devices; Improved Performance; Shorter, wider connections between dies reduce latency and boost bandwidth; Lower Power consumption; Compact interconnects result in reduced drive requirements due to lower impedance. A Vision for the Future: The introduction of 3DIC, along with 5.5D support, reflects Socionext's strong focus on advancing heterogeneous integration, bringing together multiple functions within a unified system of semiconductors and packaging elements. As demand grows for scalable, high-density, and energy-efficient platforms, especially in consumer, AI, and data center applications, 3DICs will play a pivotal role in shaping the future of semiconductor innovation.最新情報をもっと見るRecent updatesお知らせ • Apr 29Socionext Inc., Annual General Meeting, Jun 25, 2026Socionext Inc., Annual General Meeting, Jun 25, 2026.お知らせ • Mar 10Socionext Inc. to Report Fiscal Year 2026 Results on Apr 28, 2026Socionext Inc. announced that they will report fiscal year 2026 results on Apr 28, 2026お知らせ • Dec 12Socionext Inc. to Report Q3, 2026 Results on Jan 30, 2026Socionext Inc. announced that they will report Q3, 2026 results on Jan 30, 2026お知らせ • Oct 28Socionext Unveils Flexlets, A Configurable Chiplet Ecosystem to Accelerate Multi-Die Silicon InnovationSocionext Inc. introduced "Flexlets", a new class of configurable chiplets designed to advance heterogenous integration. As traditional monolithic SoC designs face physical and economic limits--reticle size constraints, yield challenges, and thermal bottlenecks- the industry is turning toward chiplet-based design, where designers can integrate their core features and interface functionalities, provided as chiplets, into a packaged device to improve performance, cost, and accelerate time-to-market. While chiplet technology opens exciting possibilities for modular designs and scalability, many current solutions are derived from fixed-function ASSPs, limiting flexibility and customization. Socionext's Flexlets overcome this by offering a configurable library of chiplet designs at the RTL level. Customers have the option to customize their designs at the RTL level to meet specific application requirements. Engineering samples of the initial Flexlet base designs, including Known Good Die (KGD), are currently in development. Socionext will initiate its first customer design this year and broaden design engagements beginning in Second Quarter calendar year 2026. Memory Expansion Flexlets: Scalable memory solutions with support for the latest DDR/LPDDR standards connected to either UCIe-S or UALink; Ethernet Controller Flexlets: Robust and high-performance networking connectivity via 224G/UE bridged to UCIe 2.0; PCIe Controller Flexlets: Seamless integration to PCIe ecosystem by bridging PCIe Gen7 128G PHY to UCIe 2. 0 with configurable lanes; Hybrid PCIe + Ethernet Controller Flexlets: A versatile range of I/O capabilities, bridging high-speed SerDes (224G/UE) to UCIe 2.2.0. All Flexlets support 2.5D/3D advanced packaging, including CoWoS, SoW-X, EMIB, and 3D stacking, process nodes (5, 3, 2nm), and industry standards, including UCIe, UALink, PCIe Gen7, and Ultra Ethernet - enabling robust interoperability across multi-vendor ecosystems. Socionext's packaging capabilities rival those of the largest chipmakers. With successful tapeouts in 2nm and 3DIC test vehicles, company offer real-world proof of engineering excellence, including support of multiple - 64 to 128 - instances of high-speed 224G SerDes in a Flexlet. In a market still lacking standardized design rule checks for large chiplet-based packages, Socionext provides the credibility and capability customers need to innovate with confidence.お知らせ • Sep 12Socionext Inc. to Report Q2, 2026 Results on Oct 31, 2025Socionext Inc. announced that they will report Q2, 2026 results on Oct 31, 2025お知らせ • Aug 28Socionext Expands 3DIC Support with Advanced 3D Die Stacking and 5.5D in Packaging PortfolioSocionext announced the availability of 3DIC support in its portfolio of well-proven capabilities for the delivery of complete solutions for consumer, AI, and HPC data center applications that include chiplets, 2.5D, 3D, and 5.5D packaging. Socionext empowers customers with a proven development process and unmatched expertise delivering high-performance, high-quality solutions that accelerate innovation and success. As a key milestone, Socionext has successfully taped out a complete packaged device leveraging TSMC's SoIC-X 3D stacking. The design combines an N3 compute die and an N5 I/O die in a face-to-face (F2F) configuration. The F2F 3D stacking approach minimizes interconnect distance, significantly reduces signal latency and power consumption compared to traditional 2D and 2.5D designs. Building on the company's experience in 2.5D designs, Socionext applies proven design experience and methodologies to 3DICs, which stack components vertically to unlock key advantages: View the 3DIC F2F and 5.5D Structure; Heterogeneous Integration: 3D ICs enable the integration of different technology nodes (3nm, 5nm, 7nm) and functions (e.g., logic, memory, interface) into a single package, allowing for a more optimally partitioned solution addressing performance, density, and cost; Higher Integration Density for a Broader Range of Applications; vertical stacking enables greater functionality in a smaller footprint--an essential advantage as traditional scaling nears its limits. This is especially valuable for space-constrained consumer devices; Improved Performance; Shorter, wider connections between dies reduce latency and boost bandwidth; Lower Power consumption; Compact interconnects result in reduced drive requirements due to lower impedance. A Vision for the Future: The introduction of 3DIC, along with 5.5D support, reflects Socionext's strong focus on advancing heterogeneous integration, bringing together multiple functions within a unified system of semiconductors and packaging elements. As demand grows for scalable, high-density, and energy-efficient platforms, especially in consumer, AI, and data center applications, 3DICs will play a pivotal role in shaping the future of semiconductor innovation.お知らせ • Jun 11Socionext Inc. to Report Q1, 2026 Results on Jul 31, 2025Socionext Inc. announced that they will report Q1, 2026 results on Jul 31, 2025お知らせ • Apr 28+ 1 more updateSocionext Inc., Annual General Meeting, Jun 26, 2025Socionext Inc., Annual General Meeting, Jun 26, 2025.お知らせ • Mar 11Socionext Inc. to Report Fiscal Year 2025 Results on Apr 28, 2025Socionext Inc. announced that they will report fiscal year 2025 results on Apr 28, 2025株主還元SOCN.FUS SemiconductorUS 市場7D11.9%0.8%1.0%1Yn/a110.2%28.7%株主還元を見る業界別リターン: SOCN.FがUS Semiconductor業界に対してどのようなパフォーマンスを示したかを判断するにはデータが不十分です。リターン対市場: SOCN.F US市場に対してどのようなパフォーマンスを示したかを判断するにはデータが不十分です。価格変動Is SOCN.F's price volatile compared to industry and market?SOCN.F volatilitySOCN.F Average Weekly Movementn/aSemiconductor Industry Average Movement11.0%Market Average Movement7.2%10% most volatile stocks in US Market16.4%10% least volatile stocks in US Market3.1%安定した株価: SOCN.Fの株価は、 US市場と比較して過去 3 か月間で変動しています。時間の経過による変動: 過去 1 年間のSOCN.Fのボラティリティの変化を判断するには データが不十分です。会社概要設立従業員CEO（最高経営責任者ウェブサイト20142,490Masahiro Koezukawww.socionext.comソシオネクスト株式会社は、システム・オン・チップ（SoC）およびSoCを中心としたソリューション／サービスの設計、開発、製造、販売を世界中で行っています。レーダーセンサー、サーバー、画像処理、映像処理、デジタルTV、デジタルサイネージ、車載、医療ヘルスケア、HDMIモジュール、IoT通信などの分野で、アプリケーションに特化した標準製品を提供している。また、カスタムSoCソリューション、開発サポート、サブシステムサービス、IPマクロサービス、設計技術、製造技術パッケージサービスも提供している。自動車、データセンター＆ネットワーキング、スマートデバイス分野にサービスを提供している。同社は2014年に設立され、横浜に本社を置いている。もっと見るSocionext Inc. 基礎のまとめSocionext の収益と売上を時価総額と比較するとどうか。SOCN.F 基礎統計学時価総額US$3.00b収益（TTM）US$54.87m売上高(TTM)US$1.26b54.7xPER（株価収益率2.4xP/SレシオSOCN.F は割高か？公正価値と評価分析を参照収益と収入最新の決算報告書（TTM）に基づく主な収益性統計SOCN.F 損益計算書（TTM）収益JP¥200.83b売上原価JP¥111.06b売上総利益JP¥89.78bその他の費用JP¥81.04b収益JP¥8.73b直近の収益報告Mar 31, 2026次回決算日該当なし一株当たり利益（EPS）49.82グロス・マージン44.70%純利益率4.35%有利子負債／自己資本比率0%SOCN.F の長期的なパフォーマンスは？過去の実績と比較を見る配当金1.8%現在の配当利回り101%配当性向View Valuation企業分析と財務データの現状データ最終更新日（UTC時間）企業分析2026/05/22 07:47終値2026/05/22 00:00収益2026/03/31年間収益2026/03/31データソース企業分析に使用したデータはS&P Global Market Intelligence LLC のものです。本レポートを作成するための分析モデルでは、以下のデータを使用しています。データは正規化されているため、ソースが利用可能になるまでに時間がかかる場合があります。パッケージデータタイムフレーム米国ソース例会社財務10年損益計算書キャッシュ・フロー計算書貸借対照表SECフォーム10-KSECフォーム10-Qアナリストのコンセンサス予想+プラス3年予想財務アナリストの目標株価アナリストリサーチレポートBlue Matrix市場価格30年株価配当、分割、措置ICEマーケットデータSECフォームS-1所有権10年トップ株主インサイダー取引SECフォーム4SECフォーム13Dマネジメント10年リーダーシップ・チーム取締役会SECフォーム10-KSECフォームDEF 14A主な進展10年会社からのお知らせSECフォーム8-K* 米国証券を対象とした例であり、非米国証券については、同等の規制書式および情報源を使用。特に断りのない限り、すべての財務データは1年ごとの期間に基づいていますが、四半期ごとに更新されます。これは、TTM（Trailing Twelve Month）またはLTM（Last Twelve Month）データとして知られています。詳細はこちら。分析モデルとスノーフレーク本レポートを生成するために使用した分析モデルの詳細は当社のGithubページでご覧いただけます。また、レポートの使用方法に関するガイドやYoutubeのチュートリアルも掲載しています。シンプリー・ウォールストリート分析モデルを設計・構築した世界トップクラスのチームについてご紹介します。業界およびセクターの指標私たちの業界とセクションの指標は、Simply Wall Stによって6時間ごとに計算されます。アナリスト筋Socionext Inc. 5 これらのアナリストのうち、弊社レポートのインプットとして使用した売上高または利益の予想を提出したのは、 。アナリストの投稿は一日中更新されます。5 アナリスト機関Takero FujiwaraCitigroup IncHiroshi TaguchiMacquarie ResearchKazuo YoshikawaMorgan Stanley2 その他のアナリストを表示
お知らせ • Apr 29Socionext Inc., Annual General Meeting, Jun 25, 2026Socionext Inc., Annual General Meeting, Jun 25, 2026.
お知らせ • Mar 10Socionext Inc. to Report Fiscal Year 2026 Results on Apr 28, 2026Socionext Inc. announced that they will report fiscal year 2026 results on Apr 28, 2026
お知らせ • Dec 12Socionext Inc. to Report Q3, 2026 Results on Jan 30, 2026Socionext Inc. announced that they will report Q3, 2026 results on Jan 30, 2026
お知らせ • Oct 28Socionext Unveils Flexlets, A Configurable Chiplet Ecosystem to Accelerate Multi-Die Silicon InnovationSocionext Inc. introduced "Flexlets", a new class of configurable chiplets designed to advance heterogenous integration. As traditional monolithic SoC designs face physical and economic limits--reticle size constraints, yield challenges, and thermal bottlenecks- the industry is turning toward chiplet-based design, where designers can integrate their core features and interface functionalities, provided as chiplets, into a packaged device to improve performance, cost, and accelerate time-to-market. While chiplet technology opens exciting possibilities for modular designs and scalability, many current solutions are derived from fixed-function ASSPs, limiting flexibility and customization. Socionext's Flexlets overcome this by offering a configurable library of chiplet designs at the RTL level. Customers have the option to customize their designs at the RTL level to meet specific application requirements. Engineering samples of the initial Flexlet base designs, including Known Good Die (KGD), are currently in development. Socionext will initiate its first customer design this year and broaden design engagements beginning in Second Quarter calendar year 2026. Memory Expansion Flexlets: Scalable memory solutions with support for the latest DDR/LPDDR standards connected to either UCIe-S or UALink; Ethernet Controller Flexlets: Robust and high-performance networking connectivity via 224G/UE bridged to UCIe 2.0; PCIe Controller Flexlets: Seamless integration to PCIe ecosystem by bridging PCIe Gen7 128G PHY to UCIe 2. 0 with configurable lanes; Hybrid PCIe + Ethernet Controller Flexlets: A versatile range of I/O capabilities, bridging high-speed SerDes (224G/UE) to UCIe 2.2.0. All Flexlets support 2.5D/3D advanced packaging, including CoWoS, SoW-X, EMIB, and 3D stacking, process nodes (5, 3, 2nm), and industry standards, including UCIe, UALink, PCIe Gen7, and Ultra Ethernet - enabling robust interoperability across multi-vendor ecosystems. Socionext's packaging capabilities rival those of the largest chipmakers. With successful tapeouts in 2nm and 3DIC test vehicles, company offer real-world proof of engineering excellence, including support of multiple - 64 to 128 - instances of high-speed 224G SerDes in a Flexlet. In a market still lacking standardized design rule checks for large chiplet-based packages, Socionext provides the credibility and capability customers need to innovate with confidence.
お知らせ • Sep 12Socionext Inc. to Report Q2, 2026 Results on Oct 31, 2025Socionext Inc. announced that they will report Q2, 2026 results on Oct 31, 2025
お知らせ • Aug 28Socionext Expands 3DIC Support with Advanced 3D Die Stacking and 5.5D in Packaging PortfolioSocionext announced the availability of 3DIC support in its portfolio of well-proven capabilities for the delivery of complete solutions for consumer, AI, and HPC data center applications that include chiplets, 2.5D, 3D, and 5.5D packaging. Socionext empowers customers with a proven development process and unmatched expertise delivering high-performance, high-quality solutions that accelerate innovation and success. As a key milestone, Socionext has successfully taped out a complete packaged device leveraging TSMC's SoIC-X 3D stacking. The design combines an N3 compute die and an N5 I/O die in a face-to-face (F2F) configuration. The F2F 3D stacking approach minimizes interconnect distance, significantly reduces signal latency and power consumption compared to traditional 2D and 2.5D designs. Building on the company's experience in 2.5D designs, Socionext applies proven design experience and methodologies to 3DICs, which stack components vertically to unlock key advantages: View the 3DIC F2F and 5.5D Structure; Heterogeneous Integration: 3D ICs enable the integration of different technology nodes (3nm, 5nm, 7nm) and functions (e.g., logic, memory, interface) into a single package, allowing for a more optimally partitioned solution addressing performance, density, and cost; Higher Integration Density for a Broader Range of Applications; vertical stacking enables greater functionality in a smaller footprint--an essential advantage as traditional scaling nears its limits. This is especially valuable for space-constrained consumer devices; Improved Performance; Shorter, wider connections between dies reduce latency and boost bandwidth; Lower Power consumption; Compact interconnects result in reduced drive requirements due to lower impedance. A Vision for the Future: The introduction of 3DIC, along with 5.5D support, reflects Socionext's strong focus on advancing heterogeneous integration, bringing together multiple functions within a unified system of semiconductors and packaging elements. As demand grows for scalable, high-density, and energy-efficient platforms, especially in consumer, AI, and data center applications, 3DICs will play a pivotal role in shaping the future of semiconductor innovation.
お知らせ • Apr 29Socionext Inc., Annual General Meeting, Jun 25, 2026Socionext Inc., Annual General Meeting, Jun 25, 2026.
お知らせ • Mar 10Socionext Inc. to Report Fiscal Year 2026 Results on Apr 28, 2026Socionext Inc. announced that they will report fiscal year 2026 results on Apr 28, 2026
お知らせ • Dec 12Socionext Inc. to Report Q3, 2026 Results on Jan 30, 2026Socionext Inc. announced that they will report Q3, 2026 results on Jan 30, 2026
お知らせ • Oct 28Socionext Unveils Flexlets, A Configurable Chiplet Ecosystem to Accelerate Multi-Die Silicon InnovationSocionext Inc. introduced "Flexlets", a new class of configurable chiplets designed to advance heterogenous integration. As traditional monolithic SoC designs face physical and economic limits--reticle size constraints, yield challenges, and thermal bottlenecks- the industry is turning toward chiplet-based design, where designers can integrate their core features and interface functionalities, provided as chiplets, into a packaged device to improve performance, cost, and accelerate time-to-market. While chiplet technology opens exciting possibilities for modular designs and scalability, many current solutions are derived from fixed-function ASSPs, limiting flexibility and customization. Socionext's Flexlets overcome this by offering a configurable library of chiplet designs at the RTL level. Customers have the option to customize their designs at the RTL level to meet specific application requirements. Engineering samples of the initial Flexlet base designs, including Known Good Die (KGD), are currently in development. Socionext will initiate its first customer design this year and broaden design engagements beginning in Second Quarter calendar year 2026. Memory Expansion Flexlets: Scalable memory solutions with support for the latest DDR/LPDDR standards connected to either UCIe-S or UALink; Ethernet Controller Flexlets: Robust and high-performance networking connectivity via 224G/UE bridged to UCIe 2.0; PCIe Controller Flexlets: Seamless integration to PCIe ecosystem by bridging PCIe Gen7 128G PHY to UCIe 2. 0 with configurable lanes; Hybrid PCIe + Ethernet Controller Flexlets: A versatile range of I/O capabilities, bridging high-speed SerDes (224G/UE) to UCIe 2.2.0. All Flexlets support 2.5D/3D advanced packaging, including CoWoS, SoW-X, EMIB, and 3D stacking, process nodes (5, 3, 2nm), and industry standards, including UCIe, UALink, PCIe Gen7, and Ultra Ethernet - enabling robust interoperability across multi-vendor ecosystems. Socionext's packaging capabilities rival those of the largest chipmakers. With successful tapeouts in 2nm and 3DIC test vehicles, company offer real-world proof of engineering excellence, including support of multiple - 64 to 128 - instances of high-speed 224G SerDes in a Flexlet. In a market still lacking standardized design rule checks for large chiplet-based packages, Socionext provides the credibility and capability customers need to innovate with confidence.
お知らせ • Sep 12Socionext Inc. to Report Q2, 2026 Results on Oct 31, 2025Socionext Inc. announced that they will report Q2, 2026 results on Oct 31, 2025
お知らせ • Aug 28Socionext Expands 3DIC Support with Advanced 3D Die Stacking and 5.5D in Packaging PortfolioSocionext announced the availability of 3DIC support in its portfolio of well-proven capabilities for the delivery of complete solutions for consumer, AI, and HPC data center applications that include chiplets, 2.5D, 3D, and 5.5D packaging. Socionext empowers customers with a proven development process and unmatched expertise delivering high-performance, high-quality solutions that accelerate innovation and success. As a key milestone, Socionext has successfully taped out a complete packaged device leveraging TSMC's SoIC-X 3D stacking. The design combines an N3 compute die and an N5 I/O die in a face-to-face (F2F) configuration. The F2F 3D stacking approach minimizes interconnect distance, significantly reduces signal latency and power consumption compared to traditional 2D and 2.5D designs. Building on the company's experience in 2.5D designs, Socionext applies proven design experience and methodologies to 3DICs, which stack components vertically to unlock key advantages: View the 3DIC F2F and 5.5D Structure; Heterogeneous Integration: 3D ICs enable the integration of different technology nodes (3nm, 5nm, 7nm) and functions (e.g., logic, memory, interface) into a single package, allowing for a more optimally partitioned solution addressing performance, density, and cost; Higher Integration Density for a Broader Range of Applications; vertical stacking enables greater functionality in a smaller footprint--an essential advantage as traditional scaling nears its limits. This is especially valuable for space-constrained consumer devices; Improved Performance; Shorter, wider connections between dies reduce latency and boost bandwidth; Lower Power consumption; Compact interconnects result in reduced drive requirements due to lower impedance. A Vision for the Future: The introduction of 3DIC, along with 5.5D support, reflects Socionext's strong focus on advancing heterogeneous integration, bringing together multiple functions within a unified system of semiconductors and packaging elements. As demand grows for scalable, high-density, and energy-efficient platforms, especially in consumer, AI, and data center applications, 3DICs will play a pivotal role in shaping the future of semiconductor innovation.
お知らせ • Jun 11Socionext Inc. to Report Q1, 2026 Results on Jul 31, 2025Socionext Inc. announced that they will report Q1, 2026 results on Jul 31, 2025
お知らせ • Apr 28+ 1 more updateSocionext Inc., Annual General Meeting, Jun 26, 2025Socionext Inc., Annual General Meeting, Jun 26, 2025.
お知らせ • Mar 11Socionext Inc. to Report Fiscal Year 2025 Results on Apr 28, 2025Socionext Inc. announced that they will report fiscal year 2025 results on Apr 28, 2025
