공시 • May 22
Advanced Micro Devices Announces Production Ramp Of Next-Generation AMD EPYC Processor Venice On TSMC 2nm Process Technology Advanced Micro Devices announced that its next-generation AMD EPYC processor, codenamed Venice, is ramping production in Taiwan on TSMC’s advanced 2nm process technology, with future plans to ramp production at TSMC’s Arizona fabrication facility. The milestone in the execution of the Advanced Micro Devices data center CPU roadmap demonstrates continued progress toward delivering the performance and energy efficiency required for next-generation cloud, enterprise and AI infrastructure. Venice is the first high-performance computing product in the industry to enter production on TSMC’s advanced 2nm process technology. As AI adoption expands from training and inference to increasingly complex agentic workloads, the CPU is becoming even more critical to scaling AI infrastructure, coordinating data movement, networking, storage, security and system orchestration across the data center. The ramp of Venice comes as Advanced Micro Devices continues to build momentum in the server market, reflecting growing customer demand for EPYC processors to power modern cloud, enterprise, HPC and AI deployments. The Venice ramp in Taiwan and plans to ramp at TSMC Arizona reflect Advanced Micro Devices’ focus on strengthening its geographically diverse advanced manufacturing footprint. By pairing next-generation EPYC processor innovation with advanced manufacturing capacity across the globe, Advanced Micro Devices is expanding the foundation needed to support customers as they deploy and scale AI infrastructure. Advanced Micro Devices also plans to extend TSMC 2nm process technology across its data center CPU roadmap with Verano, a 6th Gen EPYC processor optimized for performance-per-dollar-per-watt leadership. Designed to support cloud and AI computing workloads, Verano is expected to build on the Advanced Micro Devices EPYC platform with advanced memory innovations, including LPDDR, to deliver the CPU performance, bandwidth and efficiency required for increasingly power constrained workloads and applications. Advanced Micro Devices and TSMC’s partnership spans the technologies needed to scale modern data center computing, from TSMC 2nm process technology for next-generation CPUs to advanced packaging technologies, including TSMC’s SoIC-X and CoWoS-L, used across Advanced Micro Devices’ broader AI and data center portfolio. With Venice ramping on TSMC 2nm, Advanced Micro Devices is advancing the CPU foundation for AI infrastructure while continuing to leverage TSMC’s process and packaging leadership to deliver increasingly integrated compute platforms at scale. 공시 • May 08
Advanced Micro Devices, Inc. Provides Earnings Guidance for the Second Quarter of 2026 Advanced Micro Devices, Inc. provided earnings guidance for the second quarter of 2026. For the period, the company expects revenue to be approximately $11.2 billion, plus or minus $300 million. The mid-point of the revenue range represents year-over-year growth of approximately 46% and a sequential increase of approximately 9%. 공시 • Apr 11
Advanced Micro Devices, Inc. to Report Q1, 2026 Results on May 05, 2026 Advanced Micro Devices, Inc. announced that they will report Q1, 2026 results After-Market on May 05, 2026 공시 • Apr 09
Ultra Accelerator Link Consortium Publishes Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G Performance Ultra Accelerator Link Consortium, the industry standards organization developing the open scale-up interconnect for next-generation AI workloads, announced the ratification of the next UALink Specification, which encompasses three major additions – In-Network Compute, Chiplet Definition, and Manageability. The new specifications support the deployment of UALink solutions in multi-workload environments, while simultaneously helping improve UALink technology efficiency, performance for AI workloads and ease of implementation. The UALink Consortium provides a standardized foundation for accelerator connectivity at scale, helping drive innovation, increase deployment flexibility and support the rapidly growing performance demands of next-generation AI workloads. The new specification update is facilitated through UALink Consortium’s open governance model, which fosters innovation while enabling a robust, multi-vendor supply chain, providing system designers and cloud providers with the necessary flexibility to deploy interoperable solutions without vendor lock-in. New UALink Specifications: UALink Common Specification 2.0 introduces In-Network Compute for UALink technology, facilitating computation and communication between accelerators. Reduces latency, saves bandwidth, and improves scaling efficiency for distributed training and inference for AI solutions for complex and multi-workload environments for UALink systems. UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0 split the DL/PL Specification from the UALink Common Specification to enable UALink to move quickly as new physical layers and speeds are needed by the industry without requiring changes to the other specifications. UALink Manageability Specification 1.0 introduces UALink as a system with centralized control and management planes. Utilizes standardized protocols, modeling and APIs like gNMI, Yang, SAI and Redfish. UALink Chiplet Specification 1.0 defines the necessary information to integrate UALink technology into chiplet-based SoCs, including interfaces, form factors, flow control and chiplet management standardization. Fully compliant with the UCIe 3.0 Specification for simplified integration into existing chiplet ecosystems. All of the UALink specifications are available for public download. 공시 • Mar 30
Advanced Micro Devices, Inc., Annual General Meeting, May 13, 2026 Advanced Micro Devices, Inc., Annual General Meeting, May 13, 2026. 공시 • Mar 26
Hammer Distribution and Amd Target Uk Ai Power Wall with New Cpu-First Infrastructure Strategy Hammer Distribution and AMD are pivoting to a 'CPU-first' strategy not just as a technical choice, but as a survival tactic for UK businesses trapped in the 'time-to-power' crisis. This partnership aims to prove that the secret to unlocking AI isn't more power, but better management of the power already have. AMD EPYC processors are positioned as the critical lever for 'useful work per watt' in power-constrained environments. Hammer and AMD are highlighting that the CPU (Central Processing Unit) is the component most responsible for whether an AI stack behaves like a high-throughput pipeline or an expensive queueing system. For many enterprise workloads, such as document workflows, search augmentation (RAG), and summarization, AMD EPYC processors offer a more sustainable path to deployment. AMD's guidance also suggests that CPU-first inference is viable for models up to 20B parameters, allowing organizations to reduce accelerators, reduce power footprint, and bypass connection delays. The ability of a CPU to maximize system utilization ensuring every watt consumed produces 'useful work' is becoming a prerequisite for infrastructure investment.