View ValuationAdvanced Micro Devices 향후 성장Future 기준 점검 6/6Advanced Micro Devices (는) 각각 연간 34.8% 및 27.3% 수익과 수익이 증가할 것으로 예상됩니다. EPS는 연간 35.1% 만큼 성장할 것으로 예상됩니다. 자기자본이익률은 3년 후 26.4% 로 예상됩니다.핵심 정보34.8%이익 성장률35.05%EPS 성장률Semiconductor 이익 성장31.3%매출 성장률27.3%향후 자기자본이익률26.36%애널리스트 커버리지Good마지막 업데이트22 May 2026최근 향후 성장 업데이트공시 • May 08Advanced Micro Devices, Inc. Provides Earnings Guidance for the Second Quarter of 2026Advanced Micro Devices, Inc. provided earnings guidance for the second quarter of 2026. For the period, the company expects revenue to be approximately $11.2 billion, plus or minus $300 million. The mid-point of the revenue range represents year-over-year growth of approximately 46% and a sequential increase of approximately 9%.모든 업데이트 보기Recent updates공시 • May 22Advanced Micro Devices Announces Production Ramp Of Next-Generation AMD EPYC Processor Venice On TSMC 2nm Process TechnologyAdvanced Micro Devices announced that its next-generation AMD EPYC processor, codenamed Venice, is ramping production in Taiwan on TSMC’s advanced 2nm process technology, with future plans to ramp production at TSMC’s Arizona fabrication facility. The milestone in the execution of the Advanced Micro Devices data center CPU roadmap demonstrates continued progress toward delivering the performance and energy efficiency required for next-generation cloud, enterprise and AI infrastructure. Venice is the first high-performance computing product in the industry to enter production on TSMC’s advanced 2nm process technology. As AI adoption expands from training and inference to increasingly complex agentic workloads, the CPU is becoming even more critical to scaling AI infrastructure, coordinating data movement, networking, storage, security and system orchestration across the data center. The ramp of Venice comes as Advanced Micro Devices continues to build momentum in the server market, reflecting growing customer demand for EPYC processors to power modern cloud, enterprise, HPC and AI deployments. The Venice ramp in Taiwan and plans to ramp at TSMC Arizona reflect Advanced Micro Devices’ focus on strengthening its geographically diverse advanced manufacturing footprint. By pairing next-generation EPYC processor innovation with advanced manufacturing capacity across the globe, Advanced Micro Devices is expanding the foundation needed to support customers as they deploy and scale AI infrastructure. Advanced Micro Devices also plans to extend TSMC 2nm process technology across its data center CPU roadmap with Verano, a 6th Gen EPYC processor optimized for performance-per-dollar-per-watt leadership. Designed to support cloud and AI computing workloads, Verano is expected to build on the Advanced Micro Devices EPYC platform with advanced memory innovations, including LPDDR, to deliver the CPU performance, bandwidth and efficiency required for increasingly power constrained workloads and applications. Advanced Micro Devices and TSMC’s partnership spans the technologies needed to scale modern data center computing, from TSMC 2nm process technology for next-generation CPUs to advanced packaging technologies, including TSMC’s SoIC-X and CoWoS-L, used across Advanced Micro Devices’ broader AI and data center portfolio. With Venice ramping on TSMC 2nm, Advanced Micro Devices is advancing the CPU foundation for AI infrastructure while continuing to leverage TSMC’s process and packaging leadership to deliver increasingly integrated compute platforms at scale.공시 • May 08Advanced Micro Devices, Inc. Provides Earnings Guidance for the Second Quarter of 2026Advanced Micro Devices, Inc. provided earnings guidance for the second quarter of 2026. For the period, the company expects revenue to be approximately $11.2 billion, plus or minus $300 million. The mid-point of the revenue range represents year-over-year growth of approximately 46% and a sequential increase of approximately 9%.공시 • Apr 11Advanced Micro Devices, Inc. to Report Q1, 2026 Results on May 05, 2026Advanced Micro Devices, Inc. announced that they will report Q1, 2026 results After-Market on May 05, 2026공시 • Apr 09Ultra Accelerator Link Consortium Publishes Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G PerformanceUltra Accelerator Link Consortium, the industry standards organization developing the open scale-up interconnect for next-generation AI workloads, announced the ratification of the next UALink Specification, which encompasses three major additions – In-Network Compute, Chiplet Definition, and Manageability. The new specifications support the deployment of UALink solutions in multi-workload environments, while simultaneously helping improve UALink technology efficiency, performance for AI workloads and ease of implementation. The UALink Consortium provides a standardized foundation for accelerator connectivity at scale, helping drive innovation, increase deployment flexibility and support the rapidly growing performance demands of next-generation AI workloads. The new specification update is facilitated through UALink Consortium’s open governance model, which fosters innovation while enabling a robust, multi-vendor supply chain, providing system designers and cloud providers with the necessary flexibility to deploy interoperable solutions without vendor lock-in. New UALink Specifications: UALink Common Specification 2.0 introduces In-Network Compute for UALink technology, facilitating computation and communication between accelerators. Reduces latency, saves bandwidth, and improves scaling efficiency for distributed training and inference for AI solutions for complex and multi-workload environments for UALink systems. UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0 split the DL/PL Specification from the UALink Common Specification to enable UALink to move quickly as new physical layers and speeds are needed by the industry without requiring changes to the other specifications. UALink Manageability Specification 1.0 introduces UALink as a system with centralized control and management planes. Utilizes standardized protocols, modeling and APIs like gNMI, Yang, SAI and Redfish. UALink Chiplet Specification 1.0 defines the necessary information to integrate UALink technology into chiplet-based SoCs, including interfaces, form factors, flow control and chiplet management standardization. Fully compliant with the UCIe 3.0 Specification for simplified integration into existing chiplet ecosystems. All of the UALink specifications are available for public download.공시 • Mar 30Advanced Micro Devices, Inc., Annual General Meeting, May 13, 2026Advanced Micro Devices, Inc., Annual General Meeting, May 13, 2026.공시 • Mar 26Hammer Distribution and Amd Target Uk Ai Power Wall with New Cpu-First Infrastructure StrategyHammer Distribution and AMD are pivoting to a 'CPU-first' strategy not just as a technical choice, but as a survival tactic for UK businesses trapped in the 'time-to-power' crisis. This partnership aims to prove that the secret to unlocking AI isn't more power, but better management of the power already have. AMD EPYC processors are positioned as the critical lever for 'useful work per watt' in power-constrained environments. Hammer and AMD are highlighting that the CPU (Central Processing Unit) is the component most responsible for whether an AI stack behaves like a high-throughput pipeline or an expensive queueing system. For many enterprise workloads, such as document workflows, search augmentation (RAG), and summarization, AMD EPYC processors offer a more sustainable path to deployment. AMD's guidance also suggests that CPU-first inference is viable for models up to 20B parameters, allowing organizations to reduce accelerators, reduce power footprint, and bypass connection delays. The ability of a CPU to maximize system utilization ensuring every watt consumed produces 'useful work' is becoming a prerequisite for infrastructure investment.이익 및 매출 성장 예측SET:AMD03 - 애널리스트 향후 추정치 및 과거 재무 데이터 (USD Millions)날짜매출이익자유현금흐름영업현금흐름평균 애널리스트 수12/31/2028102,70026,10023,63725,2343012/31/202775,97817,23215,58116,9744712/31/202649,4308,8318,2609,621463/28/202637,4544,9328,5749,725N/A12/27/202534,6394,2696,7357,709N/A9/27/202532,0273,1315,4486,408N/A6/28/202529,6002,7304,0434,877N/A3/29/202527,7502,2272,7533,459N/A12/28/202425,7851,6412,4053,041N/A9/28/202424,2951,8261,5562,123N/A6/29/202423,2761,3541,3571,916N/A3/30/202422,8001,1161,1721,702N/A12/30/202322,6808541,1211,667N/A9/30/202322,1112081,3221,853N/A7/1/202321,876-251,8672,397N/A4/1/202323,0673952,5193,056N/A12/31/202223,6011,3203,1153,565N/A9/24/202222,8282,2733,4083,820N/A6/25/202221,5763,1303,3303,704N/A3/26/202218,8763,3933,3123,618N/A12/25/202116,4343,1623,2203,521N/A9/25/202114,8523,9692,9643,253N/A6/26/202113,3403,4362,4652,743N/A3/27/202111,4222,8831,7292,034N/A12/26/20209,7632,4907771,071N/A9/26/20208,646879697959N/A6/27/20207,646609611854N/A3/28/20207,245487431641N/A12/28/20196,731341N/A493N/A9/28/20196,023209N/A171N/A6/29/20195,875191N/A13N/A3/30/20196,100272N/A-72N/A12/29/20186,475337N/A34N/A9/29/20186,396280N/A238N/A6/30/20186,327239N/A231N/A3/31/20185,72281N/A204N/A12/30/20175,253-33N/A12N/A9/30/20175,019-65N/A-124N/A7/1/20174,742-532N/A-164N/A4/1/20174,618-421N/A-167N/A12/31/20164,319-498N/A81N/A9/24/20164,124-548N/A-39N/A6/25/20163,878-339N/A-124N/A3/26/20163,793-589N/A-96N/A12/26/20153,991-660N/A-226N/A9/26/20154,272-922N/A-169N/A6/27/20154,640-708N/A-95N/A더 보기애널리스트 향후 성장 전망수입 대 저축률: AMD03 의 연간 예상 수익 증가율(34.8%)이 saving rate(2.2%)보다 높습니다.수익 vs 시장: AMD03 의 연간 수익(34.8%)이 TH 시장(10.5%)보다 빠르게 성장할 것으로 예상됩니다.고성장 수익: AMD03 의 수입은 향후 3년 동안 상당히 증가할 것으로 예상됩니다.수익 대 시장: AMD03 의 수익(연간 27.3%)이 TH 시장(연간 9.7%)보다 빠르게 성장할 것으로 예상됩니다.고성장 매출: AMD03 의 수익(연간 27.3%)은 연간 20%보다 빠르게 증가할 것으로 예상됩니다.주당순이익 성장 예측향후 자기자본이익률미래 ROE: AMD03의 자본 수익률은 3년 후 26.4%로 높을 것으로 예상됩니다.성장 기업 찾아보기7D1Y7D1Y7D1YSemiconductors 산업의 고성장 기업.View Past Performance기업 분석 및 재무 데이터 상태데이터최종 업데이트 (UTC 시간)기업 분석2026/05/23 16:26종가2026/05/22 00:00수익2026/03/28연간 수익2025/12/27데이터 소스당사의 기업 분석에 사용되는 데이터는 S&P Global Market Intelligence LLC에서 제공됩니다. 아래 데이터는 이 보고서를 생성하기 위해 분석 모델에서 사용됩니다. 데이터는 정규화되므로 소스가 제공된 후 지연이 발생할 수 있습니다.패키지데이터기간미국 소스 예시 *기업 재무제표10년손익계산서현금흐름표대차대조표SEC 양식 10-KSEC 양식 10-Q분석가 컨센서스 추정치+3년재무 예측분석가 목표주가분석가 리서치 보고서Blue Matrix시장 가격30년주가배당, 분할 및 기타 조치ICE 시장 데이터SEC 양식 S-1지분 구조10년주요 주주내부자 거래SEC 양식 4SEC 양식 13D경영진10년리더십 팀이사회SEC 양식 10-KSEC 양식 DEF 14A주요 개발10년회사 공시SEC 양식 8-K* 미국 증권에 대한 예시이며, 비(非)미국 증권에는 해당 국가의 규제 서식 및 자료원을 사용합니다.별도로 명시되지 않는 한 모든 재무 데이터는 연간 기간을 기준으로 하지만 분기별로 업데이트됩니다. 이를 TTM(최근 12개월) 또는 LTM(지난 12개월) 데이터라고 합니다. 자세히 알아보기.분석 모델 및 스노우플레이크이 보고서를 생성하는 데 사용된 분석 모델에 대한 자세한 내용은 당사의 Github 페이지에서 확인하실 수 있습니다. 또한 보고서 활용 방법에 대한 가이드와 YouTube 튜토리얼도 제공합니다.Simply Wall St 분석 모델을 설계하고 구축한 세계적 수준의 팀에 대해 알아보세요.산업 및 섹터 지표산업 및 섹터 지표는 Simply Wall St가 6시간마다 계산하며, 프로세스에 대한 자세한 내용은 Github에서 확인할 수 있습니다.분석가 소스Advanced Micro Devices, Inc.는 80명의 분석가가 다루고 있습니다. 이 중 47명의 분석가가 우리 보고서에 입력 데이터로 사용되는 매출 또는 수익 추정치를 제출했습니다. 분석가의 제출 자료는 하루 종일 업데이트됩니다.분석가기관Stefan ChangAletheia Analyst Network LimitedJanco VenterArete Research Services LLPJames FontanelliArete Research Services LLP77명의 분석가 더 보기
공시 • May 08Advanced Micro Devices, Inc. Provides Earnings Guidance for the Second Quarter of 2026Advanced Micro Devices, Inc. provided earnings guidance for the second quarter of 2026. For the period, the company expects revenue to be approximately $11.2 billion, plus or minus $300 million. The mid-point of the revenue range represents year-over-year growth of approximately 46% and a sequential increase of approximately 9%.
공시 • May 22Advanced Micro Devices Announces Production Ramp Of Next-Generation AMD EPYC Processor Venice On TSMC 2nm Process TechnologyAdvanced Micro Devices announced that its next-generation AMD EPYC processor, codenamed Venice, is ramping production in Taiwan on TSMC’s advanced 2nm process technology, with future plans to ramp production at TSMC’s Arizona fabrication facility. The milestone in the execution of the Advanced Micro Devices data center CPU roadmap demonstrates continued progress toward delivering the performance and energy efficiency required for next-generation cloud, enterprise and AI infrastructure. Venice is the first high-performance computing product in the industry to enter production on TSMC’s advanced 2nm process technology. As AI adoption expands from training and inference to increasingly complex agentic workloads, the CPU is becoming even more critical to scaling AI infrastructure, coordinating data movement, networking, storage, security and system orchestration across the data center. The ramp of Venice comes as Advanced Micro Devices continues to build momentum in the server market, reflecting growing customer demand for EPYC processors to power modern cloud, enterprise, HPC and AI deployments. The Venice ramp in Taiwan and plans to ramp at TSMC Arizona reflect Advanced Micro Devices’ focus on strengthening its geographically diverse advanced manufacturing footprint. By pairing next-generation EPYC processor innovation with advanced manufacturing capacity across the globe, Advanced Micro Devices is expanding the foundation needed to support customers as they deploy and scale AI infrastructure. Advanced Micro Devices also plans to extend TSMC 2nm process technology across its data center CPU roadmap with Verano, a 6th Gen EPYC processor optimized for performance-per-dollar-per-watt leadership. Designed to support cloud and AI computing workloads, Verano is expected to build on the Advanced Micro Devices EPYC platform with advanced memory innovations, including LPDDR, to deliver the CPU performance, bandwidth and efficiency required for increasingly power constrained workloads and applications. Advanced Micro Devices and TSMC’s partnership spans the technologies needed to scale modern data center computing, from TSMC 2nm process technology for next-generation CPUs to advanced packaging technologies, including TSMC’s SoIC-X and CoWoS-L, used across Advanced Micro Devices’ broader AI and data center portfolio. With Venice ramping on TSMC 2nm, Advanced Micro Devices is advancing the CPU foundation for AI infrastructure while continuing to leverage TSMC’s process and packaging leadership to deliver increasingly integrated compute platforms at scale.
공시 • May 08Advanced Micro Devices, Inc. Provides Earnings Guidance for the Second Quarter of 2026Advanced Micro Devices, Inc. provided earnings guidance for the second quarter of 2026. For the period, the company expects revenue to be approximately $11.2 billion, plus or minus $300 million. The mid-point of the revenue range represents year-over-year growth of approximately 46% and a sequential increase of approximately 9%.
공시 • Apr 11Advanced Micro Devices, Inc. to Report Q1, 2026 Results on May 05, 2026Advanced Micro Devices, Inc. announced that they will report Q1, 2026 results After-Market on May 05, 2026
공시 • Apr 09Ultra Accelerator Link Consortium Publishes Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G PerformanceUltra Accelerator Link Consortium, the industry standards organization developing the open scale-up interconnect for next-generation AI workloads, announced the ratification of the next UALink Specification, which encompasses three major additions – In-Network Compute, Chiplet Definition, and Manageability. The new specifications support the deployment of UALink solutions in multi-workload environments, while simultaneously helping improve UALink technology efficiency, performance for AI workloads and ease of implementation. The UALink Consortium provides a standardized foundation for accelerator connectivity at scale, helping drive innovation, increase deployment flexibility and support the rapidly growing performance demands of next-generation AI workloads. The new specification update is facilitated through UALink Consortium’s open governance model, which fosters innovation while enabling a robust, multi-vendor supply chain, providing system designers and cloud providers with the necessary flexibility to deploy interoperable solutions without vendor lock-in. New UALink Specifications: UALink Common Specification 2.0 introduces In-Network Compute for UALink technology, facilitating computation and communication between accelerators. Reduces latency, saves bandwidth, and improves scaling efficiency for distributed training and inference for AI solutions for complex and multi-workload environments for UALink systems. UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0 split the DL/PL Specification from the UALink Common Specification to enable UALink to move quickly as new physical layers and speeds are needed by the industry without requiring changes to the other specifications. UALink Manageability Specification 1.0 introduces UALink as a system with centralized control and management planes. Utilizes standardized protocols, modeling and APIs like gNMI, Yang, SAI and Redfish. UALink Chiplet Specification 1.0 defines the necessary information to integrate UALink technology into chiplet-based SoCs, including interfaces, form factors, flow control and chiplet management standardization. Fully compliant with the UCIe 3.0 Specification for simplified integration into existing chiplet ecosystems. All of the UALink specifications are available for public download.
공시 • Mar 30Advanced Micro Devices, Inc., Annual General Meeting, May 13, 2026Advanced Micro Devices, Inc., Annual General Meeting, May 13, 2026.
공시 • Mar 26Hammer Distribution and Amd Target Uk Ai Power Wall with New Cpu-First Infrastructure StrategyHammer Distribution and AMD are pivoting to a 'CPU-first' strategy not just as a technical choice, but as a survival tactic for UK businesses trapped in the 'time-to-power' crisis. This partnership aims to prove that the secret to unlocking AI isn't more power, but better management of the power already have. AMD EPYC processors are positioned as the critical lever for 'useful work per watt' in power-constrained environments. Hammer and AMD are highlighting that the CPU (Central Processing Unit) is the component most responsible for whether an AI stack behaves like a high-throughput pipeline or an expensive queueing system. For many enterprise workloads, such as document workflows, search augmentation (RAG), and summarization, AMD EPYC processors offer a more sustainable path to deployment. AMD's guidance also suggests that CPU-first inference is viable for models up to 20B parameters, allowing organizations to reduce accelerators, reduce power footprint, and bypass connection delays. The ability of a CPU to maximize system utilization ensuring every watt consumed produces 'useful work' is becoming a prerequisite for infrastructure investment.