공시 • May 08
Astera Labs, Inc. Provides Earnings Guidance for the Second Quarter ending June 30, 2026 Astera Labs, Inc. provided earnings guidance for the second quarter ending June 30, 2026. For the quarter, the company expects Revenue within a range of $355 million to $365 million, GAAP diluted earnings per share of approximately $0.44 to $0.46 on weighted-average diluted shares outstanding of approximately 184 million. 공시 • May 07
Astera Labs Announces Scorpio X-Series 320 Lane Smart Fabric Switch Astera Labs, Inc. announced the Scorpio X-Series 320 Lane Smart Fabric Switch, the industry's largest open, memory-semantic fabric switch engineered to improve token economics and support large scale-up clusters with minimal latency. Astera Labs also announced an expanded Scorpio P-Series PCIe fabric switch family—now spanning 32 to 320 lane configurations—designed to give data center architects at AI labs, hyperscalers, and neo-clouds the flexibility to rapidly scale compute capacity across diverse accelerators for training and serving frontier AI models. Scorpio's software-defined architecture is designed to integrate seamlessly with leading merchant and custom silicon, enabling AI labs and hyperscalers to integrate and deploy new accelerator platforms for both training and inference. Its memory-semantic connectivity enables accelerators to access fabric resources through native load/store operations, eliminating software overhead and improving fabric efficiency at scale. Scorpio X-Series delivers simplified high-radix scale-up topologies, cutting hops and reducing end-to-end latency across the cluster. Newly introduced Hypercast and In-Network Compute engines accelerate collective operations by up to 2x to maximize GPU utilization and tokens-per-watt performance. Rounding out the family, the Scorpio P-Series complements the X-Series in front-end network and AI compute system deployments, to deliver resiliency, dynamic configurability, and broad interoperability. COSMOS software unifies the platform with purpose-built resiliency and serviceability, delivering non-disruptive firmware updates, OpenBMC management, and real-time telemetry. Hypercast and In-Network Compute are configured through COSMOS, extending its capabilities to now include platform performance optimizations. These capabilities are designed to maximize uptime, accelerator utilization, and ensure operational reliability for continuous production workloads while accelerating rack validation and compressing time-to-deployment. COSMOS extends across Astera Labs' complete rack-scale portfolio of fabric switches, copper connectivity, and optical solutions, enabling composable AI infrastructure from a single unified management software stack. The Scorpio X-Series 320 Lane Smart Fabric Switch is shipping into a merchant scale-up switch silicon market projected to reach $20 billion by 2030, with production ramp in Second Half 2026. Astera Labs will showcase the Scorpio X-Series 320 Lane and its complete rack-scale connectivity portfolio at Computex 2026 (Taipei, June 2-5), including industry-first PCIe 6 scale-up optics demonstrations leveraging COSMOS for end-to-end link management. 공시 • Apr 26
Astera Labs, Inc., Annual General Meeting, Jun 04, 2026 Astera Labs, Inc., Annual General Meeting, Jun 04, 2026. Location: offices of, astera labs, inc., at 2345 north first street, san jose, california 95131., san jose. United States 공시 • Apr 09
Ultra Accelerator Link Consortium Publishes Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G Performance Ultra Accelerator Link Consortium, the industry standards organization developing the open scale-up interconnect for next-generation AI workloads, announced the ratification of the next UALink Specification, which encompasses three major additions – In-Network Compute, Chiplet Definition, and Manageability. The new specifications support the deployment of UALink solutions in multi-workload environments, while simultaneously helping improve UALink technology efficiency, performance for AI workloads and ease of implementation. The UALink Consortium provides a standardized foundation for accelerator connectivity at scale, helping drive innovation, increase deployment flexibility and support the rapidly growing performance demands of next-generation AI workloads. The new specification update is facilitated through UALink Consortium’s open governance model, which fosters innovation while enabling a robust, multi-vendor supply chain, providing system designers and cloud providers with the necessary flexibility to deploy interoperable solutions without vendor lock-in. New UALink Specifications: UALink Common Specification 2.0 introduces In-Network Compute for UALink technology, facilitating computation and communication between accelerators. Reduces latency, saves bandwidth, and improves scaling efficiency for distributed training and inference for AI solutions for complex and multi-workload environments for UALink systems. UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0 split the DL/PL Specification from the UALink Common Specification to enable UALink to move quickly as new physical layers and speeds are needed by the industry without requiring changes to the other specifications. UALink Manageability Specification 1.0 introduces UALink as a system with centralized control and management planes. Utilizes standardized protocols, modeling and APIs like gNMI, Yang, SAI and Redfish. UALink Chiplet Specification 1.0 defines the necessary information to integrate UALink technology into chiplet-based SoCs, including interfaces, form factors, flow control and chiplet management standardization. Fully compliant with the UCIe 3.0 Specification for simplified integration into existing chiplet ecosystems. All of the UALink specifications are available for public download. 공시 • Apr 03
Astera Labs, Inc. to Report Q1, 2026 Results on May 05, 2026 Astera Labs, Inc. announced that they will report Q1, 2026 results After-Market on May 05, 2026