View Financial HealthAstera Labs 배당 및 자사주 매입배당 기준 점검 0/6Astera Labs 배당금을 지급한 기록이 없습니다.핵심 정보n/a배당 수익률-0.02%자사주 매입 수익률총 주주 수익률-0.02%미래 배당 수익률0%배당 성장률n/a다음 배당 지급일n/a배당락일n/a주당 배당금n/a배당 성향n/a최근 배당 및 자사주 매입 업데이트업데이트 없음모든 업데이트 보기Recent updates공시 • May 08Astera Labs, Inc. Provides Earnings Guidance for the Second Quarter ending June 30, 2026Astera Labs, Inc. provided earnings guidance for the second quarter ending June 30, 2026. For the quarter, the company expects Revenue within a range of $355 million to $365 million, GAAP diluted earnings per share of approximately $0.44 to $0.46 on weighted-average diluted shares outstanding of approximately 184 million.공시 • May 07Astera Labs Announces Scorpio X-Series 320 Lane Smart Fabric SwitchAstera Labs, Inc. announced the Scorpio X-Series 320 Lane Smart Fabric Switch, the industry's largest open, memory-semantic fabric switch engineered to improve token economics and support large scale-up clusters with minimal latency. Astera Labs also announced an expanded Scorpio P-Series PCIe fabric switch family—now spanning 32 to 320 lane configurations—designed to give data center architects at AI labs, hyperscalers, and neo-clouds the flexibility to rapidly scale compute capacity across diverse accelerators for training and serving frontier AI models. Scorpio's software-defined architecture is designed to integrate seamlessly with leading merchant and custom silicon, enabling AI labs and hyperscalers to integrate and deploy new accelerator platforms for both training and inference. Its memory-semantic connectivity enables accelerators to access fabric resources through native load/store operations, eliminating software overhead and improving fabric efficiency at scale. Scorpio X-Series delivers simplified high-radix scale-up topologies, cutting hops and reducing end-to-end latency across the cluster. Newly introduced Hypercast and In-Network Compute engines accelerate collective operations by up to 2x to maximize GPU utilization and tokens-per-watt performance. Rounding out the family, the Scorpio P-Series complements the X-Series in front-end network and AI compute system deployments, to deliver resiliency, dynamic configurability, and broad interoperability. COSMOS software unifies the platform with purpose-built resiliency and serviceability, delivering non-disruptive firmware updates, OpenBMC management, and real-time telemetry. Hypercast and In-Network Compute are configured through COSMOS, extending its capabilities to now include platform performance optimizations. These capabilities are designed to maximize uptime, accelerator utilization, and ensure operational reliability for continuous production workloads while accelerating rack validation and compressing time-to-deployment. COSMOS extends across Astera Labs' complete rack-scale portfolio of fabric switches, copper connectivity, and optical solutions, enabling composable AI infrastructure from a single unified management software stack. The Scorpio X-Series 320 Lane Smart Fabric Switch is shipping into a merchant scale-up switch silicon market projected to reach $20 billion by 2030, with production ramp in Second Half 2026. Astera Labs will showcase the Scorpio X-Series 320 Lane and its complete rack-scale connectivity portfolio at Computex 2026 (Taipei, June 2-5), including industry-first PCIe 6 scale-up optics demonstrations leveraging COSMOS for end-to-end link management.공시 • Apr 26Astera Labs, Inc., Annual General Meeting, Jun 04, 2026Astera Labs, Inc., Annual General Meeting, Jun 04, 2026. Location: offices of, astera labs, inc., at 2345 north first street, san jose, california 95131., san jose. United States공시 • Apr 09Ultra Accelerator Link Consortium Publishes Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G PerformanceUltra Accelerator Link Consortium, the industry standards organization developing the open scale-up interconnect for next-generation AI workloads, announced the ratification of the next UALink Specification, which encompasses three major additions – In-Network Compute, Chiplet Definition, and Manageability. The new specifications support the deployment of UALink solutions in multi-workload environments, while simultaneously helping improve UALink technology efficiency, performance for AI workloads and ease of implementation. The UALink Consortium provides a standardized foundation for accelerator connectivity at scale, helping drive innovation, increase deployment flexibility and support the rapidly growing performance demands of next-generation AI workloads. The new specification update is facilitated through UALink Consortium’s open governance model, which fosters innovation while enabling a robust, multi-vendor supply chain, providing system designers and cloud providers with the necessary flexibility to deploy interoperable solutions without vendor lock-in. New UALink Specifications: UALink Common Specification 2.0 introduces In-Network Compute for UALink technology, facilitating computation and communication between accelerators. Reduces latency, saves bandwidth, and improves scaling efficiency for distributed training and inference for AI solutions for complex and multi-workload environments for UALink systems. UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0 split the DL/PL Specification from the UALink Common Specification to enable UALink to move quickly as new physical layers and speeds are needed by the industry without requiring changes to the other specifications. UALink Manageability Specification 1.0 introduces UALink as a system with centralized control and management planes. Utilizes standardized protocols, modeling and APIs like gNMI, Yang, SAI and Redfish. UALink Chiplet Specification 1.0 defines the necessary information to integrate UALink technology into chiplet-based SoCs, including interfaces, form factors, flow control and chiplet management standardization. Fully compliant with the UCIe 3.0 Specification for simplified integration into existing chiplet ecosystems. All of the UALink specifications are available for public download.공시 • Apr 03Astera Labs, Inc. to Report Q1, 2026 Results on May 05, 2026Astera Labs, Inc. announced that they will report Q1, 2026 results After-Market on May 05, 2026공시 • Feb 11+ 1 more updateAstera Labs, Inc. Announces Chief Financial Officer Changes, Effective March 2, 2026Astera Labs, Inc. appointed Desmond Lynch, age 46, as Chief Financial Officer, effective March 2, 2026. Desmond Lynch previously served as Senior Vice President, Finance and Chief Financial Officer of Rambus Inc. from August 2022 until February 2026 and served as the Vice President of Finance and Investor Relations of Rambus from 2020 until 2022. In addition, Desmond Lynch served as Vice President, Finance of Knowles Corporation, an audio solutions company, from 2019 to 2020. Previously, Desmond Lynch served as Vice President, Finance/Senior Director, Financial Planning and Analysis at Renesas Electronics Corporation/Integrated Device Technology, Inc., an analog and mixed signal semiconductor company, from 2016 to 2019. Desmond Lynch also served as Director, Financial Planning and Analysis at Atmel Corporation, a semiconductor company, from 2010 to 2016, prior to its acquisition by Microchip Technology. Desmond Lynch received a bachelor's degree in Accounting and Finance from the University of Glasgow, Scotland, in 2000, and is a Chartered Accountant with the Institute of Chartered Accountants of Scotland. On February 4, 2026, Michael Tate notified the Company of his retirement as Chief Financial Officer of the Company, effective March 2, 2026. Mr. Tate remains an employee of the Company and will transition to a role as Strategic Advisor to the CEO until September 1, 2026.지급의 안정성과 성장배당 데이터 가져오는 중안정적인 배당: 과거에 ALABD 의 주당 배당금이 안정적이었는지 판단하기에는 데이터가 부족합니다.배당금 증가: ALABD 의 배당금 지급이 증가했는지 판단하기에는 데이터가 부족합니다.배당 수익률 vs 시장Astera Labs 배당 수익률 vs 시장ALABD의 배당 수익률은 시장과 어떻게 비교되나요?구분배당 수익률회사 (ALABD)n/a시장 하위 25% (AR)0%시장 상위 25% (AR)0%업계 평균 (Semiconductor)0%분석가 예측 (ALABD) (최대 3년)0%주목할만한 배당금: 회사가 최근 지급을 보고하지 않았기 때문에 하위 25%의 배당금 지급자에 대해 ALABD 의 배당 수익률을 평가할 수 없습니다.고배당: 회사가 최근 지급을 보고하지 않았기 때문에 배당금 지급자의 상위 25%에 대해 ALABD 의 배당 수익률을 평가할 수 없습니다.주주 대상 이익 배당수익 보장: 배당금 지급이 수익으로 충당되는지 확인하기 위해 ALABD 의 지급 비율을 계산하기에는 데이터가 부족합니다.주주 현금 배당현금 흐름 범위: ALABD 에서 지급을 보고하지 않았기 때문에 배당 지속 가능성을 계산할 수 없습니다.높은 배당을 제공하는 우량 기업 찾기7D1Y7D1Y7D1YAR 시장에서 배당이 강한 기업.View Management기업 분석 및 재무 데이터 상태데이터최종 업데이트 (UTC 시간)기업 분석2026/05/21 20:48종가2026/02/26 00:00수익2026/03/31연간 수익2025/12/31데이터 소스당사의 기업 분석에 사용되는 데이터는 S&P Global Market Intelligence LLC에서 제공됩니다. 아래 데이터는 이 보고서를 생성하기 위해 분석 모델에서 사용됩니다. 데이터는 정규화되므로 소스가 제공된 후 지연이 발생할 수 있습니다.패키지데이터기간미국 소스 예시 *기업 재무제표10년손익계산서현금흐름표대차대조표SEC 양식 10-KSEC 양식 10-Q분석가 컨센서스 추정치+3년재무 예측분석가 목표주가분석가 리서치 보고서Blue Matrix시장 가격30년주가배당, 분할 및 기타 조치ICE 시장 데이터SEC 양식 S-1지분 구조10년주요 주주내부자 거래SEC 양식 4SEC 양식 13D경영진10년리더십 팀이사회SEC 양식 10-KSEC 양식 DEF 14A주요 개발10년회사 공시SEC 양식 8-K* 미국 증권에 대한 예시이며, 비(非)미국 증권에는 해당 국가의 규제 서식 및 자료원을 사용합니다.별도로 명시되지 않는 한 모든 재무 데이터는 연간 기간을 기준으로 하지만 분기별로 업데이트됩니다. 이를 TTM(최근 12개월) 또는 LTM(지난 12개월) 데이터라고 합니다. 자세히 알아보기.분석 모델 및 스노우플레이크이 보고서를 생성하는 데 사용된 분석 모델에 대한 자세한 내용은 당사의 Github 페이지에서 확인하실 수 있습니다. 또한 보고서 활용 방법에 대한 가이드와 YouTube 튜토리얼도 제공합니다.Simply Wall St 분석 모델을 설계하고 구축한 세계적 수준의 팀에 대해 알아보세요.산업 및 섹터 지표산업 및 섹터 지표는 Simply Wall St가 6시간마다 계산하며, 프로세스에 대한 자세한 내용은 Github에서 확인할 수 있습니다.분석가 소스Astera Labs, Inc.는 30명의 분석가가 다루고 있습니다. 이 중 24명의 분석가가 우리 보고서에 입력 데이터로 사용되는 매출 또는 수익 추정치를 제출했습니다. 분석가의 제출 자료는 하루 종일 업데이트됩니다.분석가기관Thomas O'MalleyBarclaysKarl AckermanBNP ParibasVivek AryaBofA Global Research27명의 분석가 더 보기
공시 • May 08Astera Labs, Inc. Provides Earnings Guidance for the Second Quarter ending June 30, 2026Astera Labs, Inc. provided earnings guidance for the second quarter ending June 30, 2026. For the quarter, the company expects Revenue within a range of $355 million to $365 million, GAAP diluted earnings per share of approximately $0.44 to $0.46 on weighted-average diluted shares outstanding of approximately 184 million.
공시 • May 07Astera Labs Announces Scorpio X-Series 320 Lane Smart Fabric SwitchAstera Labs, Inc. announced the Scorpio X-Series 320 Lane Smart Fabric Switch, the industry's largest open, memory-semantic fabric switch engineered to improve token economics and support large scale-up clusters with minimal latency. Astera Labs also announced an expanded Scorpio P-Series PCIe fabric switch family—now spanning 32 to 320 lane configurations—designed to give data center architects at AI labs, hyperscalers, and neo-clouds the flexibility to rapidly scale compute capacity across diverse accelerators for training and serving frontier AI models. Scorpio's software-defined architecture is designed to integrate seamlessly with leading merchant and custom silicon, enabling AI labs and hyperscalers to integrate and deploy new accelerator platforms for both training and inference. Its memory-semantic connectivity enables accelerators to access fabric resources through native load/store operations, eliminating software overhead and improving fabric efficiency at scale. Scorpio X-Series delivers simplified high-radix scale-up topologies, cutting hops and reducing end-to-end latency across the cluster. Newly introduced Hypercast and In-Network Compute engines accelerate collective operations by up to 2x to maximize GPU utilization and tokens-per-watt performance. Rounding out the family, the Scorpio P-Series complements the X-Series in front-end network and AI compute system deployments, to deliver resiliency, dynamic configurability, and broad interoperability. COSMOS software unifies the platform with purpose-built resiliency and serviceability, delivering non-disruptive firmware updates, OpenBMC management, and real-time telemetry. Hypercast and In-Network Compute are configured through COSMOS, extending its capabilities to now include platform performance optimizations. These capabilities are designed to maximize uptime, accelerator utilization, and ensure operational reliability for continuous production workloads while accelerating rack validation and compressing time-to-deployment. COSMOS extends across Astera Labs' complete rack-scale portfolio of fabric switches, copper connectivity, and optical solutions, enabling composable AI infrastructure from a single unified management software stack. The Scorpio X-Series 320 Lane Smart Fabric Switch is shipping into a merchant scale-up switch silicon market projected to reach $20 billion by 2030, with production ramp in Second Half 2026. Astera Labs will showcase the Scorpio X-Series 320 Lane and its complete rack-scale connectivity portfolio at Computex 2026 (Taipei, June 2-5), including industry-first PCIe 6 scale-up optics demonstrations leveraging COSMOS for end-to-end link management.
공시 • Apr 26Astera Labs, Inc., Annual General Meeting, Jun 04, 2026Astera Labs, Inc., Annual General Meeting, Jun 04, 2026. Location: offices of, astera labs, inc., at 2345 north first street, san jose, california 95131., san jose. United States
공시 • Apr 09Ultra Accelerator Link Consortium Publishes Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G PerformanceUltra Accelerator Link Consortium, the industry standards organization developing the open scale-up interconnect for next-generation AI workloads, announced the ratification of the next UALink Specification, which encompasses three major additions – In-Network Compute, Chiplet Definition, and Manageability. The new specifications support the deployment of UALink solutions in multi-workload environments, while simultaneously helping improve UALink technology efficiency, performance for AI workloads and ease of implementation. The UALink Consortium provides a standardized foundation for accelerator connectivity at scale, helping drive innovation, increase deployment flexibility and support the rapidly growing performance demands of next-generation AI workloads. The new specification update is facilitated through UALink Consortium’s open governance model, which fosters innovation while enabling a robust, multi-vendor supply chain, providing system designers and cloud providers with the necessary flexibility to deploy interoperable solutions without vendor lock-in. New UALink Specifications: UALink Common Specification 2.0 introduces In-Network Compute for UALink technology, facilitating computation and communication between accelerators. Reduces latency, saves bandwidth, and improves scaling efficiency for distributed training and inference for AI solutions for complex and multi-workload environments for UALink systems. UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0 split the DL/PL Specification from the UALink Common Specification to enable UALink to move quickly as new physical layers and speeds are needed by the industry without requiring changes to the other specifications. UALink Manageability Specification 1.0 introduces UALink as a system with centralized control and management planes. Utilizes standardized protocols, modeling and APIs like gNMI, Yang, SAI and Redfish. UALink Chiplet Specification 1.0 defines the necessary information to integrate UALink technology into chiplet-based SoCs, including interfaces, form factors, flow control and chiplet management standardization. Fully compliant with the UCIe 3.0 Specification for simplified integration into existing chiplet ecosystems. All of the UALink specifications are available for public download.
공시 • Apr 03Astera Labs, Inc. to Report Q1, 2026 Results on May 05, 2026Astera Labs, Inc. announced that they will report Q1, 2026 results After-Market on May 05, 2026
공시 • Feb 11+ 1 more updateAstera Labs, Inc. Announces Chief Financial Officer Changes, Effective March 2, 2026Astera Labs, Inc. appointed Desmond Lynch, age 46, as Chief Financial Officer, effective March 2, 2026. Desmond Lynch previously served as Senior Vice President, Finance and Chief Financial Officer of Rambus Inc. from August 2022 until February 2026 and served as the Vice President of Finance and Investor Relations of Rambus from 2020 until 2022. In addition, Desmond Lynch served as Vice President, Finance of Knowles Corporation, an audio solutions company, from 2019 to 2020. Previously, Desmond Lynch served as Vice President, Finance/Senior Director, Financial Planning and Analysis at Renesas Electronics Corporation/Integrated Device Technology, Inc., an analog and mixed signal semiconductor company, from 2016 to 2019. Desmond Lynch also served as Director, Financial Planning and Analysis at Atmel Corporation, a semiconductor company, from 2010 to 2016, prior to its acquisition by Microchip Technology. Desmond Lynch received a bachelor's degree in Accounting and Finance from the University of Glasgow, Scotland, in 2000, and is a Chartered Accountant with the Institute of Chartered Accountants of Scotland. On February 4, 2026, Michael Tate notified the Company of his retirement as Chief Financial Officer of the Company, effective March 2, 2026. Mr. Tate remains an employee of the Company and will transition to a role as Strategic Advisor to the CEO until September 1, 2026.