View Future GrowthAdvanced Micro Devices 過去の業績過去 基準チェック /56Advanced Micro Devicesは、平均年間0.9%の収益成長を遂げていますが、 Semiconductor業界の収益は、年間 減少しています。収益は、平均年間0.3% 16.9%収益成長率で 成長しています。 Advanced Micro Devicesの自己資本利益率は7.7%であり、純利益率は13.2%です。主要情報0.89%収益成長率-9.06%EPS成長率Semiconductor 業界の成長23.83%収益成長率16.90%株主資本利益率7.65%ネット・マージン13.17%前回の決算情報28 Mar 2026最近の業績更新お知らせ • Apr 11Advanced Micro Devices, Inc. to Report Q1, 2026 Results on May 05, 2026Advanced Micro Devices, Inc. announced that they will report Q1, 2026 results After-Market on May 05, 2026すべての更新を表示Recent updatesお知らせ • May 22Advanced Micro Devices Announces Production Ramp Of Next-Generation AMD EPYC Processor Venice On TSMC 2nm Process TechnologyAdvanced Micro Devices announced that its next-generation AMD EPYC processor, codenamed Venice, is ramping production in Taiwan on TSMC’s advanced 2nm process technology, with future plans to ramp production at TSMC’s Arizona fabrication facility. The milestone in the execution of the Advanced Micro Devices data center CPU roadmap demonstrates continued progress toward delivering the performance and energy efficiency required for next-generation cloud, enterprise and AI infrastructure. Venice is the first high-performance computing product in the industry to enter production on TSMC’s advanced 2nm process technology. As AI adoption expands from training and inference to increasingly complex agentic workloads, the CPU is becoming even more critical to scaling AI infrastructure, coordinating data movement, networking, storage, security and system orchestration across the data center. The ramp of Venice comes as Advanced Micro Devices continues to build momentum in the server market, reflecting growing customer demand for EPYC processors to power modern cloud, enterprise, HPC and AI deployments. The Venice ramp in Taiwan and plans to ramp at TSMC Arizona reflect Advanced Micro Devices’ focus on strengthening its geographically diverse advanced manufacturing footprint. By pairing next-generation EPYC processor innovation with advanced manufacturing capacity across the globe, Advanced Micro Devices is expanding the foundation needed to support customers as they deploy and scale AI infrastructure. Advanced Micro Devices also plans to extend TSMC 2nm process technology across its data center CPU roadmap with Verano, a 6th Gen EPYC processor optimized for performance-per-dollar-per-watt leadership. Designed to support cloud and AI computing workloads, Verano is expected to build on the Advanced Micro Devices EPYC platform with advanced memory innovations, including LPDDR, to deliver the CPU performance, bandwidth and efficiency required for increasingly power constrained workloads and applications. Advanced Micro Devices and TSMC’s partnership spans the technologies needed to scale modern data center computing, from TSMC 2nm process technology for next-generation CPUs to advanced packaging technologies, including TSMC’s SoIC-X and CoWoS-L, used across Advanced Micro Devices’ broader AI and data center portfolio. With Venice ramping on TSMC 2nm, Advanced Micro Devices is advancing the CPU foundation for AI infrastructure while continuing to leverage TSMC’s process and packaging leadership to deliver increasingly integrated compute platforms at scale.お知らせ • May 08Advanced Micro Devices, Inc. Provides Earnings Guidance for the Second Quarter of 2026Advanced Micro Devices, Inc. provided earnings guidance for the second quarter of 2026. For the period, the company expects revenue to be approximately $11.2 billion, plus or minus $300 million. The mid-point of the revenue range represents year-over-year growth of approximately 46% and a sequential increase of approximately 9%.お知らせ • Apr 11Advanced Micro Devices, Inc. to Report Q1, 2026 Results on May 05, 2026Advanced Micro Devices, Inc. announced that they will report Q1, 2026 results After-Market on May 05, 2026お知らせ • Apr 09Ultra Accelerator Link Consortium Publishes Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G PerformanceUltra Accelerator Link Consortium, the industry standards organization developing the open scale-up interconnect for next-generation AI workloads, announced the ratification of the next UALink Specification, which encompasses three major additions – In-Network Compute, Chiplet Definition, and Manageability. The new specifications support the deployment of UALink solutions in multi-workload environments, while simultaneously helping improve UALink technology efficiency, performance for AI workloads and ease of implementation. The UALink Consortium provides a standardized foundation for accelerator connectivity at scale, helping drive innovation, increase deployment flexibility and support the rapidly growing performance demands of next-generation AI workloads. The new specification update is facilitated through UALink Consortium’s open governance model, which fosters innovation while enabling a robust, multi-vendor supply chain, providing system designers and cloud providers with the necessary flexibility to deploy interoperable solutions without vendor lock-in. New UALink Specifications: UALink Common Specification 2.0 introduces In-Network Compute for UALink technology, facilitating computation and communication between accelerators. Reduces latency, saves bandwidth, and improves scaling efficiency for distributed training and inference for AI solutions for complex and multi-workload environments for UALink systems. UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0 split the DL/PL Specification from the UALink Common Specification to enable UALink to move quickly as new physical layers and speeds are needed by the industry without requiring changes to the other specifications. UALink Manageability Specification 1.0 introduces UALink as a system with centralized control and management planes. Utilizes standardized protocols, modeling and APIs like gNMI, Yang, SAI and Redfish. UALink Chiplet Specification 1.0 defines the necessary information to integrate UALink technology into chiplet-based SoCs, including interfaces, form factors, flow control and chiplet management standardization. Fully compliant with the UCIe 3.0 Specification for simplified integration into existing chiplet ecosystems. All of the UALink specifications are available for public download.お知らせ • Mar 30Advanced Micro Devices, Inc., Annual General Meeting, May 13, 2026Advanced Micro Devices, Inc., Annual General Meeting, May 13, 2026.お知らせ • Mar 26Hammer Distribution and Amd Target Uk Ai Power Wall with New Cpu-First Infrastructure StrategyHammer Distribution and AMD are pivoting to a 'CPU-first' strategy not just as a technical choice, but as a survival tactic for UK businesses trapped in the 'time-to-power' crisis. This partnership aims to prove that the secret to unlocking AI isn't more power, but better management of the power already have. AMD EPYC processors are positioned as the critical lever for 'useful work per watt' in power-constrained environments. Hammer and AMD are highlighting that the CPU (Central Processing Unit) is the component most responsible for whether an AI stack behaves like a high-throughput pipeline or an expensive queueing system. For many enterprise workloads, such as document workflows, search augmentation (RAG), and summarization, AMD EPYC processors offer a more sustainable path to deployment. AMD's guidance also suggests that CPU-first inference is viable for models up to 20B parameters, allowing organizations to reduce accelerators, reduce power footprint, and bypass connection delays. The ability of a CPU to maximize system utilization ensuring every watt consumed produces 'useful work' is becoming a prerequisite for infrastructure investment.収支内訳Advanced Micro Devices の稼ぎ方とお金の使い方。LTMベースの直近の報告された収益に基づく。収益と収入の歴史SET:AMD03 収益、費用、利益 ( )USD Millions日付収益収益G+A経費研究開発費28 Mar 2637,4544,9324,4648,76027 Dec 2534,6394,2694,0978,09127 Sep 2532,0273,1313,7287,47328 Jun 2529,6002,7303,3666,97029 Mar 2527,7502,2273,0146,65928 Dec 2425,7851,6412,7356,45628 Sep 2424,2951,8262,5986,25529 Jun 2423,2761,3542,4676,12630 Mar 2422,8001,1162,3745,98630 Dec 2322,6808542,3185,87230 Sep 2322,1112082,2985,72701 Jul 2321,876-252,2795,49901 Apr 2323,0673952,3245,35631 Dec 2223,6011,3202,3365,00524 Sep 2222,8282,2732,1914,45025 Jun 2221,5763,1301,9773,93626 Mar 2218,8763,3931,7263,29525 Dec 2116,4343,1621,4482,84525 Sep 2114,8523,9691,3112,60726 Jun 2113,3403,4361,2412,35027 Mar 2111,4222,8831,1152,15126 Dec 209,7632,4909951,98326 Sep 208,6468798931,80527 Jun 207,6466098051,70328 Mar 207,2454877791,61628 Dec 196,7313417501,54728 Sep 196,0232096821,52329 Jun 195,8751916451,48030 Mar 196,1002725981,46429 Dec 186,4753375621,43429 Sep 186,3962805581,38330 Jun 186,3272395421,34031 Mar 185,722815271,26830 Dec 175,253-335161,19630 Sep 175,019-655031,14001 Jul 174,742-5324881,07901 Apr 174,618-4214781,03731 Dec 164,319-4984661,00824 Sep 164,124-54844897325 Jun 163,878-33943995526 Mar 163,793-58945694726 Dec 153,991-66048294726 Sep 154,272-92251795627 Jun 154,640-708559993質の高い収益: AMD03は 高品質の収益 を持っています。利益率の向上: AMD03の現在の純利益率 (13.2%)は、昨年(8%)よりも高くなっています。フリー・キャッシュフローと収益の比較過去の収益成長分析収益動向: AMD03の収益は過去 5 年間で年間0.9%増加しました。成長の加速: AMD03の過去 1 年間の収益成長率 ( 122.1% ) は、5 年間の平均 ( 年間0.9%を上回っています。収益対業界: AMD03の過去 1 年間の収益成長率 ( 122.1% ) はSemiconductor業界5.9%を上回りました。株主資本利益率高いROE: AMD03の 自己資本利益率 ( 7.7% ) は 低い とみなされます。総資産利益率使用総資本利益率過去の好業績企業の発掘7D1Y7D1Y7D1YSemiconductors 、過去の業績が好調な企業。View Financial Health企業分析と財務データの現状データ最終更新日（UTC時間）企業分析2026/05/23 19:46終値2026/05/22 00:00収益2026/03/28年間収益2025/12/27データソース企業分析に使用したデータはS&P Global Market Intelligence LLC のものです。本レポートを作成するための分析モデルでは、以下のデータを使用しています。データは正規化されているため、ソースが利用可能になるまでに時間がかかる場合があります。パッケージデータタイムフレーム米国ソース例会社財務10年損益計算書キャッシュ・フロー計算書貸借対照表SECフォーム10-KSECフォーム10-Qアナリストのコンセンサス予想+プラス3年予想財務アナリストの目標株価アナリストリサーチレポートBlue Matrix市場価格30年株価配当、分割、措置ICEマーケットデータSECフォームS-1所有権10年トップ株主インサイダー取引SECフォーム4SECフォーム13Dマネジメント10年リーダーシップ・チーム取締役会SECフォーム10-KSECフォームDEF 14A主な進展10年会社からのお知らせSECフォーム8-K* 米国証券を対象とした例であり、非米国証券については、同等の規制書式および情報源を使用。特に断りのない限り、すべての財務データは1年ごとの期間に基づいていますが、四半期ごとに更新されます。これは、TTM（Trailing Twelve Month）またはLTM（Last Twelve Month）データとして知られています。詳細はこちら。分析モデルとスノーフレーク本レポートを生成するために使用した分析モデルの詳細は当社のGithubページでご覧いただけます。また、レポートの使用方法に関するガイドやYoutubeのチュートリアルも掲載しています。シンプリー・ウォールストリート分析モデルを設計・構築した世界トップクラスのチームについてご紹介します。業界およびセクターの指標私たちの業界とセクションの指標は、Simply Wall Stによって6時間ごとに計算されます。アナリスト筋Advanced Micro Devices, Inc. 47 これらのアナリストのうち、弊社レポートのインプットとして使用した売上高または利益の予想を提出したのは、 。アナリストの投稿は一日中更新されます。80 アナリスト機関Stefan ChangAletheia Analyst Network LimitedJanco VenterArete Research Services LLPJames FontanelliArete Research Services LLP77 その他のアナリストを表示
お知らせ • Apr 11Advanced Micro Devices, Inc. to Report Q1, 2026 Results on May 05, 2026Advanced Micro Devices, Inc. announced that they will report Q1, 2026 results After-Market on May 05, 2026
お知らせ • May 22Advanced Micro Devices Announces Production Ramp Of Next-Generation AMD EPYC Processor Venice On TSMC 2nm Process TechnologyAdvanced Micro Devices announced that its next-generation AMD EPYC processor, codenamed Venice, is ramping production in Taiwan on TSMC’s advanced 2nm process technology, with future plans to ramp production at TSMC’s Arizona fabrication facility. The milestone in the execution of the Advanced Micro Devices data center CPU roadmap demonstrates continued progress toward delivering the performance and energy efficiency required for next-generation cloud, enterprise and AI infrastructure. Venice is the first high-performance computing product in the industry to enter production on TSMC’s advanced 2nm process technology. As AI adoption expands from training and inference to increasingly complex agentic workloads, the CPU is becoming even more critical to scaling AI infrastructure, coordinating data movement, networking, storage, security and system orchestration across the data center. The ramp of Venice comes as Advanced Micro Devices continues to build momentum in the server market, reflecting growing customer demand for EPYC processors to power modern cloud, enterprise, HPC and AI deployments. The Venice ramp in Taiwan and plans to ramp at TSMC Arizona reflect Advanced Micro Devices’ focus on strengthening its geographically diverse advanced manufacturing footprint. By pairing next-generation EPYC processor innovation with advanced manufacturing capacity across the globe, Advanced Micro Devices is expanding the foundation needed to support customers as they deploy and scale AI infrastructure. Advanced Micro Devices also plans to extend TSMC 2nm process technology across its data center CPU roadmap with Verano, a 6th Gen EPYC processor optimized for performance-per-dollar-per-watt leadership. Designed to support cloud and AI computing workloads, Verano is expected to build on the Advanced Micro Devices EPYC platform with advanced memory innovations, including LPDDR, to deliver the CPU performance, bandwidth and efficiency required for increasingly power constrained workloads and applications. Advanced Micro Devices and TSMC’s partnership spans the technologies needed to scale modern data center computing, from TSMC 2nm process technology for next-generation CPUs to advanced packaging technologies, including TSMC’s SoIC-X and CoWoS-L, used across Advanced Micro Devices’ broader AI and data center portfolio. With Venice ramping on TSMC 2nm, Advanced Micro Devices is advancing the CPU foundation for AI infrastructure while continuing to leverage TSMC’s process and packaging leadership to deliver increasingly integrated compute platforms at scale.
お知らせ • May 08Advanced Micro Devices, Inc. Provides Earnings Guidance for the Second Quarter of 2026Advanced Micro Devices, Inc. provided earnings guidance for the second quarter of 2026. For the period, the company expects revenue to be approximately $11.2 billion, plus or minus $300 million. The mid-point of the revenue range represents year-over-year growth of approximately 46% and a sequential increase of approximately 9%.
お知らせ • Apr 11Advanced Micro Devices, Inc. to Report Q1, 2026 Results on May 05, 2026Advanced Micro Devices, Inc. announced that they will report Q1, 2026 results After-Market on May 05, 2026
お知らせ • Apr 09Ultra Accelerator Link Consortium Publishes Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G PerformanceUltra Accelerator Link Consortium, the industry standards organization developing the open scale-up interconnect for next-generation AI workloads, announced the ratification of the next UALink Specification, which encompasses three major additions – In-Network Compute, Chiplet Definition, and Manageability. The new specifications support the deployment of UALink solutions in multi-workload environments, while simultaneously helping improve UALink technology efficiency, performance for AI workloads and ease of implementation. The UALink Consortium provides a standardized foundation for accelerator connectivity at scale, helping drive innovation, increase deployment flexibility and support the rapidly growing performance demands of next-generation AI workloads. The new specification update is facilitated through UALink Consortium’s open governance model, which fosters innovation while enabling a robust, multi-vendor supply chain, providing system designers and cloud providers with the necessary flexibility to deploy interoperable solutions without vendor lock-in. New UALink Specifications: UALink Common Specification 2.0 introduces In-Network Compute for UALink technology, facilitating computation and communication between accelerators. Reduces latency, saves bandwidth, and improves scaling efficiency for distributed training and inference for AI solutions for complex and multi-workload environments for UALink systems. UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0 split the DL/PL Specification from the UALink Common Specification to enable UALink to move quickly as new physical layers and speeds are needed by the industry without requiring changes to the other specifications. UALink Manageability Specification 1.0 introduces UALink as a system with centralized control and management planes. Utilizes standardized protocols, modeling and APIs like gNMI, Yang, SAI and Redfish. UALink Chiplet Specification 1.0 defines the necessary information to integrate UALink technology into chiplet-based SoCs, including interfaces, form factors, flow control and chiplet management standardization. Fully compliant with the UCIe 3.0 Specification for simplified integration into existing chiplet ecosystems. All of the UALink specifications are available for public download.
お知らせ • Mar 30Advanced Micro Devices, Inc., Annual General Meeting, May 13, 2026Advanced Micro Devices, Inc., Annual General Meeting, May 13, 2026.
お知らせ • Mar 26Hammer Distribution and Amd Target Uk Ai Power Wall with New Cpu-First Infrastructure StrategyHammer Distribution and AMD are pivoting to a 'CPU-first' strategy not just as a technical choice, but as a survival tactic for UK businesses trapped in the 'time-to-power' crisis. This partnership aims to prove that the secret to unlocking AI isn't more power, but better management of the power already have. AMD EPYC processors are positioned as the critical lever for 'useful work per watt' in power-constrained environments. Hammer and AMD are highlighting that the CPU (Central Processing Unit) is the component most responsible for whether an AI stack behaves like a high-throughput pipeline or an expensive queueing system. For many enterprise workloads, such as document workflows, search augmentation (RAG), and summarization, AMD EPYC processors offer a more sustainable path to deployment. AMD's guidance also suggests that CPU-first inference is viable for models up to 20B parameters, allowing organizations to reduce accelerators, reduce power footprint, and bypass connection delays. The ability of a CPU to maximize system utilization ensuring every watt consumed produces 'useful work' is becoming a prerequisite for infrastructure investment.