View Financial HealthAdvanced Micro Devices 配当と自社株買い配当金 基準チェック /06Advanced Micro Devices配当金を支払った記録がありません。主要情報n/a配当利回り0.2%バイバック利回り総株主利回り0.2%将来の配当利回り0%配当成長n/a次回配当支払日n/a配当落ち日n/a一株当たり配当金n/a配当性向n/a最近の配当と自社株買いの更新更新なしすべての更新を表示Recent updatesお知らせ • May 22Advanced Micro Devices Announces Production Ramp Of Next-Generation AMD EPYC Processor Venice On TSMC 2nm Process TechnologyAdvanced Micro Devices announced that its next-generation AMD EPYC processor, codenamed Venice, is ramping production in Taiwan on TSMC’s advanced 2nm process technology, with future plans to ramp production at TSMC’s Arizona fabrication facility. The milestone in the execution of the Advanced Micro Devices data center CPU roadmap demonstrates continued progress toward delivering the performance and energy efficiency required for next-generation cloud, enterprise and AI infrastructure. Venice is the first high-performance computing product in the industry to enter production on TSMC’s advanced 2nm process technology. As AI adoption expands from training and inference to increasingly complex agentic workloads, the CPU is becoming even more critical to scaling AI infrastructure, coordinating data movement, networking, storage, security and system orchestration across the data center. The ramp of Venice comes as Advanced Micro Devices continues to build momentum in the server market, reflecting growing customer demand for EPYC processors to power modern cloud, enterprise, HPC and AI deployments. The Venice ramp in Taiwan and plans to ramp at TSMC Arizona reflect Advanced Micro Devices’ focus on strengthening its geographically diverse advanced manufacturing footprint. By pairing next-generation EPYC processor innovation with advanced manufacturing capacity across the globe, Advanced Micro Devices is expanding the foundation needed to support customers as they deploy and scale AI infrastructure. Advanced Micro Devices also plans to extend TSMC 2nm process technology across its data center CPU roadmap with Verano, a 6th Gen EPYC processor optimized for performance-per-dollar-per-watt leadership. Designed to support cloud and AI computing workloads, Verano is expected to build on the Advanced Micro Devices EPYC platform with advanced memory innovations, including LPDDR, to deliver the CPU performance, bandwidth and efficiency required for increasingly power constrained workloads and applications. Advanced Micro Devices and TSMC’s partnership spans the technologies needed to scale modern data center computing, from TSMC 2nm process technology for next-generation CPUs to advanced packaging technologies, including TSMC’s SoIC-X and CoWoS-L, used across Advanced Micro Devices’ broader AI and data center portfolio. With Venice ramping on TSMC 2nm, Advanced Micro Devices is advancing the CPU foundation for AI infrastructure while continuing to leverage TSMC’s process and packaging leadership to deliver increasingly integrated compute platforms at scale.お知らせ • May 08Advanced Micro Devices, Inc. Provides Earnings Guidance for the Second Quarter of 2026Advanced Micro Devices, Inc. provided earnings guidance for the second quarter of 2026. For the period, the company expects revenue to be approximately $11.2 billion, plus or minus $300 million. The mid-point of the revenue range represents year-over-year growth of approximately 46% and a sequential increase of approximately 9%.お知らせ • Apr 11Advanced Micro Devices, Inc. to Report Q1, 2026 Results on May 05, 2026Advanced Micro Devices, Inc. announced that they will report Q1, 2026 results After-Market on May 05, 2026お知らせ • Apr 09Ultra Accelerator Link Consortium Publishes Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G PerformanceUltra Accelerator Link Consortium, the industry standards organization developing the open scale-up interconnect for next-generation AI workloads, announced the ratification of the next UALink Specification, which encompasses three major additions – In-Network Compute, Chiplet Definition, and Manageability. The new specifications support the deployment of UALink solutions in multi-workload environments, while simultaneously helping improve UALink technology efficiency, performance for AI workloads and ease of implementation. The UALink Consortium provides a standardized foundation for accelerator connectivity at scale, helping drive innovation, increase deployment flexibility and support the rapidly growing performance demands of next-generation AI workloads. The new specification update is facilitated through UALink Consortium’s open governance model, which fosters innovation while enabling a robust, multi-vendor supply chain, providing system designers and cloud providers with the necessary flexibility to deploy interoperable solutions without vendor lock-in. New UALink Specifications: UALink Common Specification 2.0 introduces In-Network Compute for UALink technology, facilitating computation and communication between accelerators. Reduces latency, saves bandwidth, and improves scaling efficiency for distributed training and inference for AI solutions for complex and multi-workload environments for UALink systems. UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0 split the DL/PL Specification from the UALink Common Specification to enable UALink to move quickly as new physical layers and speeds are needed by the industry without requiring changes to the other specifications. UALink Manageability Specification 1.0 introduces UALink as a system with centralized control and management planes. Utilizes standardized protocols, modeling and APIs like gNMI, Yang, SAI and Redfish. UALink Chiplet Specification 1.0 defines the necessary information to integrate UALink technology into chiplet-based SoCs, including interfaces, form factors, flow control and chiplet management standardization. Fully compliant with the UCIe 3.0 Specification for simplified integration into existing chiplet ecosystems. All of the UALink specifications are available for public download.お知らせ • Mar 30Advanced Micro Devices, Inc., Annual General Meeting, May 13, 2026Advanced Micro Devices, Inc., Annual General Meeting, May 13, 2026.お知らせ • Mar 26Hammer Distribution and Amd Target Uk Ai Power Wall with New Cpu-First Infrastructure StrategyHammer Distribution and AMD are pivoting to a 'CPU-first' strategy not just as a technical choice, but as a survival tactic for UK businesses trapped in the 'time-to-power' crisis. This partnership aims to prove that the secret to unlocking AI isn't more power, but better management of the power already have. AMD EPYC processors are positioned as the critical lever for 'useful work per watt' in power-constrained environments. Hammer and AMD are highlighting that the CPU (Central Processing Unit) is the component most responsible for whether an AI stack behaves like a high-throughput pipeline or an expensive queueing system. For many enterprise workloads, such as document workflows, search augmentation (RAG), and summarization, AMD EPYC processors offer a more sustainable path to deployment. AMD's guidance also suggests that CPU-first inference is viable for models up to 20B parameters, allowing organizations to reduce accelerators, reduce power footprint, and bypass connection delays. The ability of a CPU to maximize system utilization ensuring every watt consumed produces 'useful work' is becoming a prerequisite for infrastructure investment.決済の安定と成長配当データの取得安定した配当: AMD03の 1 株当たり配当が過去に安定していたかどうかを判断するにはデータが不十分です。増加する配当: AMD03の配当金が増加しているかどうかを判断するにはデータが不十分です。配当利回り対市場Advanced Micro Devices 配当利回り対市場AMD03 配当利回りは市場と比べてどうか？セグメント配当利回り会社 (AMD03)n/a市場下位25% (TH)3.4%市場トップ25% (TH)7.5%業界平均 (Semiconductor)0.7%アナリスト予想 (AMD03) (最長3年)0%注目すべき配当: AMD03は最近配当金を報告していないため、配当金支払者の下位 25% に対して同社の配当利回りを評価することはできません。高配当: AMD03は最近配当金を報告していないため、配当金支払者の上位 25% に対して同社の配当利回りを評価することはできません。株主への利益配当収益カバレッジ: AMD03の 配当性向 を計算して配当金の支払いが利益で賄われているかどうかを判断するにはデータが不十分です。株主配当金キャッシュフローカバレッジ: AMD03が配当金を報告していないため、配当金の持続可能性を計算できません。高配当企業の発掘7D1Y7D1Y7D1YTH 市場の強力な配当支払い企業。View Management企業分析と財務データの現状データ最終更新日（UTC時間）企業分析2026/05/23 19:46終値2026/05/22 00:00収益2026/03/28年間収益2025/12/27データソース企業分析に使用したデータはS&P Global Market Intelligence LLC のものです。本レポートを作成するための分析モデルでは、以下のデータを使用しています。データは正規化されているため、ソースが利用可能になるまでに時間がかかる場合があります。パッケージデータタイムフレーム米国ソース例会社財務10年損益計算書キャッシュ・フロー計算書貸借対照表SECフォーム10-KSECフォーム10-Qアナリストのコンセンサス予想+プラス3年予想財務アナリストの目標株価アナリストリサーチレポートBlue Matrix市場価格30年株価配当、分割、措置ICEマーケットデータSECフォームS-1所有権10年トップ株主インサイダー取引SECフォーム4SECフォーム13Dマネジメント10年リーダーシップ・チーム取締役会SECフォーム10-KSECフォームDEF 14A主な進展10年会社からのお知らせSECフォーム8-K* 米国証券を対象とした例であり、非米国証券については、同等の規制書式および情報源を使用。特に断りのない限り、すべての財務データは1年ごとの期間に基づいていますが、四半期ごとに更新されます。これは、TTM（Trailing Twelve Month）またはLTM（Last Twelve Month）データとして知られています。詳細はこちら。分析モデルとスノーフレーク本レポートを生成するために使用した分析モデルの詳細は当社のGithubページでご覧いただけます。また、レポートの使用方法に関するガイドやYoutubeのチュートリアルも掲載しています。シンプリー・ウォールストリート分析モデルを設計・構築した世界トップクラスのチームについてご紹介します。業界およびセクターの指標私たちの業界とセクションの指標は、Simply Wall Stによって6時間ごとに計算されます。アナリスト筋Advanced Micro Devices, Inc. 47 これらのアナリストのうち、弊社レポートのインプットとして使用した売上高または利益の予想を提出したのは、 。アナリストの投稿は一日中更新されます。80 アナリスト機関Stefan ChangAletheia Analyst Network LimitedJanco VenterArete Research Services LLPJames FontanelliArete Research Services LLP77 その他のアナリストを表示
お知らせ • May 22Advanced Micro Devices Announces Production Ramp Of Next-Generation AMD EPYC Processor Venice On TSMC 2nm Process TechnologyAdvanced Micro Devices announced that its next-generation AMD EPYC processor, codenamed Venice, is ramping production in Taiwan on TSMC’s advanced 2nm process technology, with future plans to ramp production at TSMC’s Arizona fabrication facility. The milestone in the execution of the Advanced Micro Devices data center CPU roadmap demonstrates continued progress toward delivering the performance and energy efficiency required for next-generation cloud, enterprise and AI infrastructure. Venice is the first high-performance computing product in the industry to enter production on TSMC’s advanced 2nm process technology. As AI adoption expands from training and inference to increasingly complex agentic workloads, the CPU is becoming even more critical to scaling AI infrastructure, coordinating data movement, networking, storage, security and system orchestration across the data center. The ramp of Venice comes as Advanced Micro Devices continues to build momentum in the server market, reflecting growing customer demand for EPYC processors to power modern cloud, enterprise, HPC and AI deployments. The Venice ramp in Taiwan and plans to ramp at TSMC Arizona reflect Advanced Micro Devices’ focus on strengthening its geographically diverse advanced manufacturing footprint. By pairing next-generation EPYC processor innovation with advanced manufacturing capacity across the globe, Advanced Micro Devices is expanding the foundation needed to support customers as they deploy and scale AI infrastructure. Advanced Micro Devices also plans to extend TSMC 2nm process technology across its data center CPU roadmap with Verano, a 6th Gen EPYC processor optimized for performance-per-dollar-per-watt leadership. Designed to support cloud and AI computing workloads, Verano is expected to build on the Advanced Micro Devices EPYC platform with advanced memory innovations, including LPDDR, to deliver the CPU performance, bandwidth and efficiency required for increasingly power constrained workloads and applications. Advanced Micro Devices and TSMC’s partnership spans the technologies needed to scale modern data center computing, from TSMC 2nm process technology for next-generation CPUs to advanced packaging technologies, including TSMC’s SoIC-X and CoWoS-L, used across Advanced Micro Devices’ broader AI and data center portfolio. With Venice ramping on TSMC 2nm, Advanced Micro Devices is advancing the CPU foundation for AI infrastructure while continuing to leverage TSMC’s process and packaging leadership to deliver increasingly integrated compute platforms at scale.
お知らせ • May 08Advanced Micro Devices, Inc. Provides Earnings Guidance for the Second Quarter of 2026Advanced Micro Devices, Inc. provided earnings guidance for the second quarter of 2026. For the period, the company expects revenue to be approximately $11.2 billion, plus or minus $300 million. The mid-point of the revenue range represents year-over-year growth of approximately 46% and a sequential increase of approximately 9%.
お知らせ • Apr 11Advanced Micro Devices, Inc. to Report Q1, 2026 Results on May 05, 2026Advanced Micro Devices, Inc. announced that they will report Q1, 2026 results After-Market on May 05, 2026
お知らせ • Apr 09Ultra Accelerator Link Consortium Publishes Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G PerformanceUltra Accelerator Link Consortium, the industry standards organization developing the open scale-up interconnect for next-generation AI workloads, announced the ratification of the next UALink Specification, which encompasses three major additions – In-Network Compute, Chiplet Definition, and Manageability. The new specifications support the deployment of UALink solutions in multi-workload environments, while simultaneously helping improve UALink technology efficiency, performance for AI workloads and ease of implementation. The UALink Consortium provides a standardized foundation for accelerator connectivity at scale, helping drive innovation, increase deployment flexibility and support the rapidly growing performance demands of next-generation AI workloads. The new specification update is facilitated through UALink Consortium’s open governance model, which fosters innovation while enabling a robust, multi-vendor supply chain, providing system designers and cloud providers with the necessary flexibility to deploy interoperable solutions without vendor lock-in. New UALink Specifications: UALink Common Specification 2.0 introduces In-Network Compute for UALink technology, facilitating computation and communication between accelerators. Reduces latency, saves bandwidth, and improves scaling efficiency for distributed training and inference for AI solutions for complex and multi-workload environments for UALink systems. UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0 split the DL/PL Specification from the UALink Common Specification to enable UALink to move quickly as new physical layers and speeds are needed by the industry without requiring changes to the other specifications. UALink Manageability Specification 1.0 introduces UALink as a system with centralized control and management planes. Utilizes standardized protocols, modeling and APIs like gNMI, Yang, SAI and Redfish. UALink Chiplet Specification 1.0 defines the necessary information to integrate UALink technology into chiplet-based SoCs, including interfaces, form factors, flow control and chiplet management standardization. Fully compliant with the UCIe 3.0 Specification for simplified integration into existing chiplet ecosystems. All of the UALink specifications are available for public download.
お知らせ • Mar 30Advanced Micro Devices, Inc., Annual General Meeting, May 13, 2026Advanced Micro Devices, Inc., Annual General Meeting, May 13, 2026.
お知らせ • Mar 26Hammer Distribution and Amd Target Uk Ai Power Wall with New Cpu-First Infrastructure StrategyHammer Distribution and AMD are pivoting to a 'CPU-first' strategy not just as a technical choice, but as a survival tactic for UK businesses trapped in the 'time-to-power' crisis. This partnership aims to prove that the secret to unlocking AI isn't more power, but better management of the power already have. AMD EPYC processors are positioned as the critical lever for 'useful work per watt' in power-constrained environments. Hammer and AMD are highlighting that the CPU (Central Processing Unit) is the component most responsible for whether an AI stack behaves like a high-throughput pipeline or an expensive queueing system. For many enterprise workloads, such as document workflows, search augmentation (RAG), and summarization, AMD EPYC processors offer a more sustainable path to deployment. AMD's guidance also suggests that CPU-first inference is viable for models up to 20B parameters, allowing organizations to reduce accelerators, reduce power footprint, and bypass connection delays. The ability of a CPU to maximize system utilization ensuring every watt consumed produces 'useful work' is becoming a prerequisite for infrastructure investment.