Ankündigung • Mar 10
Andes Technology Corporation, Annual General Meeting, May 28, 2026 Andes Technology Corporation, Annual General Meeting, May 28, 2026, at 10:00 Taipei Standard Time. Location: 4 floor no,1, kung yeh tung 2nd rd., hsinchu science park, hsinchu city Taiwan Ankündigung • Oct 27
Andes Technology Corporation has filed a Follow-on Equity Offering in the amount of TWD 118.35 million. Andes Technology Corporation has filed a Follow-on Equity Offering in the amount of TWD 118.35 million.
Security Name: Shares
Security Type: Common Stock
Securities Offered: 450,000
Price\Range: TWD 263 Ankündigung • May 06
Andes Technology Corporation has filed a Follow-on Equity Offering. Andes Technology Corporation has filed a Follow-on Equity Offering.
Security Name: Common Shares
Security Type: Common Stock
Securities Offered: 1,000,000
Security Name: Common Shares
Security Type: Common Stock
Securities Offered: 4,000,000
Transaction Features: Rights Offering Ankündigung • Apr 29
Andes Technology Corporation to Report Q1, 2025 Results on May 05, 2025 Andes Technology Corporation announced that they will report Q1, 2025 results at 9:00 AM, Taipei Standard Time on May 05, 2025 Ankündigung • Apr 24
Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based Platform Andes Technology in collaboration with Imagination Technologies announced the successful demonstration of Android 15 (Vanilla Ice Cream) running on a high-performance RISC-V-based hardware system. This achievement highlights the growing potential of RISC-V as a platform for rich operating systems and advanced graphical applications. The demonstration leverages Andes' Voyager Board, powered by its Qilai SoC, in combination with Imagination's GPU integrated within a graphics card. Together, the companies are showcasing a highly capable, fully operational Android system built on open hardware standards. The demonstration will be featured at the 2025 Andes RISC-V CON Silicon Valley, taking place on April 29th at the Doubletree by Hilton Hotel in San Jose. At the heart of the demonstration is a Voyager Development Board, built around Andes' 7nm Qilai RISC-V SoC. Key features include: Quad-core Andes AX45MP running at 2.2 GHz, powering the Android kernel. This processor is Andes' most widely licensed for rich OS environments, offering a strong balance of performance, power efficiency, and area optimization. NX27V Vector Processor at 1.5 GHz, featuring a 512-bit Vector Processing Unit (VPU) designed for parallel data processing -- ideal for machine learning, image processing, and signal processing workloads. Graphics performance is enables by the Imagination BXT-32-1024 GPU integrated into the graphics card, which delivers: 48 Gpixels/sec fill rate; 1.5 TFLOPS (FP32) of floating-point performance; Dual 4K display support at 60 fps; Full compatibility with modern graphics and compute APIs including OpenGL ES 3.2, Vulkan 1.3, and OpenCL 3.0. This powerful combination ensures a responsive and immersive Android experience on RISC-V hardware. This demonstration marks a significant milestone in the evolution of RISC-V and GPU integration. The powerful combination of Andes' RISC-V CPU cores and Imagination's cutting-edge GPU capabilities opens up new possibilities for embedded, AI and high-performance Android applications. Ankündigung • Mar 07
Andes Technology Corporation, Annual General Meeting, May 29, 2025 Andes Technology Corporation, Annual General Meeting, May 29, 2025. Location: 4 floor no,1, kung yeh tung 2nd rd., hsinchu science park, hsinchu city Taiwan Ankündigung • Feb 27
Andes Technology Corporation to Report Q4, 2024 Results on Mar 06, 2025 Andes Technology Corporation announced that they will report Q4, 2024 results on Mar 06, 2025 Ankündigung • Nov 01
Andes Technology Corporation to Report Q3, 2024 Results on Nov 08, 2024 Andes Technology Corporation announced that they will report Q3, 2024 results on Nov 08, 2024 Ankündigung • Oct 18
Andes Announces the AndesCore AX66 supporting RVA23, Multi-cluster, Hypervisor and Android Andes Technology announced the AndesCore AX66 out-of-order superscalar multicore processor IP supporting the RVA23 profile. The AX66 is the 2nd member of the high-performance out-of-order AX60 series. Built on the success of the AX65 with the same 13-stage pipeline, 4-wide decode, and 8-wide out-of-order execution, the AX66 introduces many new features, including Vector and Vector Crypto support, Hypervisor and AIA, Multi-Cluster support with CHI, and RVA23 profile support. AX66's versatile capabilities on performance scalability, multimedia, security, and virtualization makes it an ideal main processor in high-performance Linux and Android applications such as edge/data center AI, infotainment, networking, and vision/camera applications. The AX66 boosts the SpecInt2006 performance over the 1st generation AX65 by more than 15%. Each core has 64KB private L1 instruction and data caches and up to 1MB private L2 cache, and each cluster contains up to 8 cores and a shared L3 cache up to 32MB. Besides the IO coherence interface already in the AX65, the AX66 adds a Coherence Hub Interface (CHI) for multi-cluster coherence. With the CHI interface support, the company can use much more AX66 CPUs to work together in the same cache-coherent domain. Together with the Hypervisor, AIA and optional IOMMU technologies, the AX66 can fully virtualize the entire multi-cluster CPU subsystem for resource sharing and security. Moreover, the AX66 supports the RISC-V standard external debug and instruction trace interfaces to facilitate fast system development, analysis and debugging. The AndesCore™? AX 66 is to be available for lead customers in Fourth Quarter 2024 through the early access program and for general customers in 2025. Ankündigung • Jul 30
Andes Technology Corporation to Report Q2, 2024 Results on Aug 06, 2024 Andes Technology Corporation announced that they will report Q2, 2024 results on Aug 06, 2024 Ankündigung • May 01
Andes Technology Corporation to Report Q1, 2024 Results on May 07, 2024 Andes Technology Corporation announced that they will report Q1, 2024 results on May 07, 2024 Ankündigung • Mar 07
Andes Technology Corporation, Annual General Meeting, May 24, 2024 Andes Technology Corporation, Annual General Meeting, May 24, 2024. Location: No.1, Gongye E. 2nd Rd., Hsinchu Science Park (4F, Meeting Room: Bach) Taiwan Agenda: To consider Report 2023 business report; to consider Audit Committee's review report; to consider Report on 2023 employees' profit sharing bonus and directors' compensation; to consider Report on the 2023 cash dividend distribution; to consider Amendment to the Company's" Sustainable Development Best Practice; to consider Adoption of the 2023 business report and financial statements; and to consider other matters. Ankündigung • Jan 05
Andes Technology Corporation Announces General Availability of the New RISC-V Out-Of-Order Superscalar Multicore Processor, the AndesCore™ AX65 Andes Technology Corporation announced general availability of the high-performance AndesCore™ AX65 out-of-order superscalar multicore processor IP. The AX65 is the first of the high-performance out-of-order AX60 series. Equipped with 13-stage pipeline, 4-wide decode, 8-wide out-of-order execution, AX65 targets the Linux application processor sockets of computing, networking, and high-end controllers. It also received "Best IP/Processor of the Year" Award from EE Times Asia last December. Andes has been very successful on the embedded controllers and high-performance AI vector processors. As RISC-V ecosystem for Linux is getting matured, the demand for high-performance RISC-V processors for general-purpose applications rises. Andes takes this opportunity to introduce the AX65 to complete its comprehensive CPU lineup, spanning from low-power embedded solutions to high-end Out-of-Order processors. Customers who develop complex SOC can now use AX65 as the primary Linux application processor, the AX45MPV/NX27V for the vector/DSP processing and the N25/N225 processors as the resource and power manager. Leveraging the entire range of CPUs in the AndesCore™? families enables customers to streamline their development process, benefit from integrated support, and significantly reduce development cost. The AX65 operates at speeds exceeding 2.0GHz on a 12nm process, boasting a SpecInt2006 score of 8.25 per GHz -- outperforming the Cortex A75 with an efficient memory hierarchy. It also supports up to 8-core cache coherence with maximum 8MB shared cache. The AX65 is fully compliant with the RISC-V RVA22 profile, ensuring compatibility with operating systems and software within the RISC-V ecosystem. On the security side, AX65 supports Enhanced PMP (ePMP) for further securing memory accesses, and K (scalar cryptography) extension for accelerating AES and SHA crypto operations. For running Linux OS, the AX65 supports VIPT L1 instruction cache, SV48 virtual address space, and 2-level TLB with simultaneous hardware page walkers. It also incorporates branch prediction mechanism with TAGE-L algorithm, return address stack and 2-level branch target buffer. The AX65 can be used as an application processor in networking applications like Wi-Fi, 5Gnr, and O-RAN, as well as in edge computing and industrial PCs. Furthermore, it is well-suited for serving as the primary controller processor in embedded applications. Ankündigung • Oct 18
Andes Technology Unveils Andes D23 and N225 Cores Pioneering the Next Generation of Compact, Performant, and Secure RISC-V Processor Technology Andes Technology announced the release of its latest innovation - the AndesCore™? D23 and N225 RISC-V processors. Specifically designed to cater to the dynamic needs of the Internet of Things (IoT) and embedded systems, these cores epitomize Andes' unwavering commitment to delivering cutting-edge technology for the interconnected world. The D23 and N225 cores have been meticulously engineered with compactness, performance-efficiency, low-power consumption, flexibility, and security as top priorities. These cores empower IoT and embedded chip and device manufacturers to meet the burgeoning demands of a rapidly evolving market while minimizing power usage and ensuring robust security. Andes announced the popular N22, a 2-stage pipeline AndesCore implementing RV32I/EMAC ISA back in February 2019, targeting deeply embedded processing and having a performance of 3.95 Coremark/MHz and 1.8 DMIPS/MHz. The D23 and N 225 are revamped designs with a new microarchitecture and the latest RISC-V extensions to offer better performance, smaller code size, and more security support. They provide a good migration path for customers looking to upgrade their N22 designs or kick-off a new design. Common Key Features of AndesCore D23 and N225: Latest RISC-V Extensions Support: The N225 implements the RV32 IMACBZce non-privileged extensions as well as Machine/User modes and Enhanced Physical Memory Protection (ePMP). The D23 additionally supports the FDKP extensions (Single/Double-Precision Floating-Point, Scalar Crypto and Packed SIMD/DSP draft), and CMO (Cache Management Operations) extension. The D23 is also incorporated with Supervisor mode and its associated PMP (sPMP) for higher security. High Performance: Both cores achieve performance in their class, boasting outstanding benchmark scores such as 4.55 (D23) and 4.4 (N225) Coremark/MHz, and 2.08 (D23) and 1.92 (N225) DMIPS/MHz, respectively. They are capable of operating at high frequencies across various technology nodes such as near 800 MHz at 28nm, providing the necessary computing power for edge IoT devices with ever-increasing performance and feature demands. Power Management: Both cores support advanced power management technologies such as PowerBrake and Wait-For-Interrupt (WFI) and Wait-For-Event (WFE), ensuring prolonged battery life for many types of untethered IoT devices. Small Code Size: The N22 already offers code size with Andes CoDense™? technology. With the addition of the new RISC-V Zce code size reduction extension, the D23 and N225 further reduce 4.4% code size for the Embench-IoT benchmark, compared to the N22. This provides additional memory cost-saving for Andes customers. Flexibility: Both cores offer extensive configurability, including optimized multipliers for performance or area, optional static or dynamic branch prediction, various combinations of privilege modes, instruction and data. Local memories with sizes from 1 KB to 512 MB, and 2-wire or 4-wire JTAG debug interface. Designers can tailor these features to address their specific application requirements. In addition to the above-mentioned shared features and latest RISC-V extensions, the D23 core boasts additional capabilities, including built-in instruction and data cache, and ECC soft error protection for all cache and local memories. It can also seamlessly integrate with the powerful ACE™? (Andes Custom Extension) to support custom instructions for Domain-Specific Acceleration (DSA) and has a roadmap to include a functional safety derivative. These expanded capabilities open up opportunities for the D23 to serve a wider range of segments in automotive and industrial control applications. Ankündigung • Sep 09
Andes Technology Announces General Availability of the New Andescore Risc-V Multicore Vector Processor Ax45mpv Andes Technology announced general availability of the high-performance AndesCore™? AX45MPV multicore vector processor IP. The AX45MPV is the third generation of the award winning AndesCore™? vector processor series. Equipped with powerful RISC-V vector processing and parallel execution capability, it targets the applications with large volumes of data such as ADAS, AI inference and training, AR/VR, multimedia, robotics, and signal processing. Andes and Meta started collaboration on datacenter AI with RISC-V vector core from early 2019. Andes later unveiled the AndesCore™? NX27V, marking a significant milestone as the industry's first commercial RISC-V vector processor core with the capability of generating up to 4 512-bit vector (VLEN) results per cycle, at the end of 2019. It immediately attracted the attention of worldwide SoC design teams working on AI accelerators, and has landed over a dozen datacenter AI projects. Since then, the RISC-V vector processor cores have become the choice for ML and AI chip vendors. With the goal to further raise the compute density, the AX45MPV extends the capabilities of the dual-issue 8-stage pipeline, Linux support and multicore of the AX45MP with the powerful vector processing unit inherited and enhanced from its predecessor, the NX27V. While the AX45MPV is essentially a Linux application processor with datacenter grade AI capabilities, its support for Linux and multicore can be left out to form an efficient and powerful compute processor in processing elements (PEs) of a large compute array. The AX45MPV also supports the latest ACE (Andes Custom Extension™?), which facilitates customers to create their own RISC-V styled vector instructions. For example, ACE can be used to accelerate nonlinear math functions such as SoftMax on Transformer AI. Some customers from Asia and North America have already licensed the AX45MPV, and more are evaluating it. Their applications cover a wide range from the cloud to the edge. The AX45MPV standard product package, without Linux support, is available immediately. Its advanced product package will come with Linux support and will be available in Fourth Quarter 2023. 
