Announcement • Apr 28
Advantest Corporation, Annual General Meeting, Jul 31, 2026 Advantest Corporation, Annual General Meeting, Jul 31, 2026. Announcement • Apr 24
Advantest Corporation Introduces Pin Scale 5000B Digital Test Solution To Extend Capabilities Of V93000 EXA Scale Test Platform Advantest Corporation announced Pin Scale 5000B, an enhanced digital test solution for the V93000 EXA Scale Platform designed to address the growing test requirements of advanced artificial intelligence (AI) and high-performance computing (HPC) devices. AI and HPC semiconductor capabilities and complexity are growing swiftly, driven by advanced process nodes, heterogeneous integration and chiplet-based architectures. These devices require significantly higher structural and functional test coverage and processing of rapidly increasing volumes of test data. The Pin Scale 5000B card significantly expands available vector memory, offering deep and scalable storage capacity aligned with industry demands. Hardware and software facilitate optimal memory usage in chiplet-based architectures, reducing customers’ overall consumption and associated costs while addressing evolving memory requirements for the future. The new card also enables customers to efficiently scale their existing test programs and hardware configurations in response to evolving device requirements. This solution is engineered to accommodate contemporary scan fabric architectures, enabling concurrent testing of multiple IP cores using a streaming approach. Its new hardware capabilities allow test results to be observed across multiple cores within a single test pattern execution, enabling instantaneous insights into error distribution among the cores. These capabilities help improve structural coverage and core-level visibility, significantly reducing test times and cost-of-test. The Pin Scale 5000B delivers high-bandwidth test access, offering data rates up to 5 Gbps through the proven pin electronics architecture of the Pin Scale 5000. Pin Scale 5000B is a fully compatible superset of the established Pin Scale 5000, complementing the V93000 portfolio. The Pin Scale 5000B digital test instrument is now ramping with key customers. Announcement • Mar 14
Advantest Corporation to Report Fiscal Year 2026 Results on Apr 27, 2026 Advantest Corporation announced that they will report fiscal year 2026 results at 3:30 PM, Tokyo Standard Time on Apr 27, 2026 Announcement • Jan 28
Advantest Corporation Revises Consolidated Earnings Guidance for the Year Ending March 31, 2026 Advantest Corporation revised consolidated earnings guidance for the year ending March 31, 2026. For the year, the company expects the net sales to be JPY 1,070,000 million, operating income to be JPY 454,000 million, net income of JPY 328,500 million, net income attributable to owners of the parent to be JPY 328,500 million or basic earnings per share to be JPY 452.34 against net sales to be JPY 950.0 billion, operating income to be JPY 374.0 billion, net income of JPY 275.0 billion. Announcement • Dec 12
Advantest Corporation to Report Q3, 2026 Results on Jan 28, 2026 Advantest Corporation announced that they will report Q3, 2026 results on Jan 28, 2026 Announcement • Oct 30
Advantest Corporation Unveils MTe - Unified, Scalable Test Platform for Power Semiconductor Devices Advantest Corporation announced the MTe power test platform. The cutting-edge MTe redefines test efficiency and scalability to address test requirements for the fast-growing power semiconductor market. Increasing market demand for electrification across automotive, industrial, renewable energy, telecommunication and data infrastructure applications is pushing semiconductor manufacturers to achieve higher performance and lower cost of test (CoT). The MTe platform responds to these needs by combining modular hardware architecture, ultimate system scalability and advanced digital control, redefining the standard in power semiconductor test performance and efficiency. Designed with Advantest technology, MTe provides significant footprint reduction and optimized resource distribution without performance degradation--a key enabler to attract major IDM and OSAT players. The MTe platform is able to address emerging wide-bandgap semiconductor (e.g., SiC and GaN) challenges, as well as the integration of digital IP cores on power devices (e.g., IPM and IPD), providing high bandwidth capture, best-in-class gate driver control, dynamic (and short-circuit) test up to 10kA, and flexible high-voltage digital capabilities. Aligned with Advantest's history of providing scalable test platforms, MTe distributed computing architecture provides significant multisite test efficiency, enabling a high-parallel-test solution with optimized throughput. The MTe platform is now available worldwide. Early evaluations by customers in automotive and industrial power applications have confirmed significant productivity and throughput gains compared with legacy testers. Announcement • Sep 30
Advantest Corporation Launches Power Optimization Solution to Enhance Energy Efficiency and Sustainability in Semiconductor Testing Advantest Corporation launched its new Advantest Power Optimization Solution (APOS) for the V93000 system-on-chip (SoC) test platform. Designed to improve energy efficiency without compromising performance, the APOS software enables foundries and outsourced semiconductor assembly and test (OSAT) providers to achieve their sustainability goals while reducing operational costs. With energy consumption representing a significant operational expense, semiconductor companies are actively seeking ways to optimize power usage. Developed by Advantest's production service team, APOS provides a comprehensive power-saving framework, allowing users to visualize and manage V93000 tester power consumption in real time, helping to lower electricity costs while maintaining high throughput and test accuracy. In addition, APOS contributes to corporate sustainability efforts by improving tester energy efficiency and thereby reducing the overall carbon footprint. The APOS software has already been installed on V93000 test systems at multiple customer sites, yielding positive results in reducing test costs and strengthening environmental initiatives. Smart power management - APOS expands Advantest's Smart TestCell (STC) ecosystem, which leverages advanced automation and resource management to enable smart semiconductor manufacturing. APOS automatically enables/disables selected test cards based on real-world tester scenarios, reducing unnecessary power consumption. Real-time visualization - APOS Client Display provides an intuitive dashboard with real-time insights into power usage and card type, status and quantity used. Centralized control and reporting - The APOS Dashboard integrates with the Testcell Central System (TCS) Server Web Dashboard to centrally manage test-floor power-saving data and utilizes the history record for reporting and further optimization. The Advantest Power Optimization solution for the V93000 test platform is available now to the global market. Announcement • Sep 18
Advantest Corporation Expands 7038 System-Level Test Platform with Right-Sized Single Test Rack Solution for High-Volume Manufacturing Advantest Corporation announced its 7038 Single Test Rack (STR) system-level test (SLT) and burn-in test (BI) solution. The 7038 STR extends the company's proven 7038 SLT platform with a lower-cost architecture optimized for slot-based automated test solutions, enabling right-sized SLT deployment in the production of artificial intelligence (AI), high-performance compute (HPC), automotive, and other low- to mid-volume devices. The new 7038 STR delivers liquid-cooled thermal management of up to 1.4 kW per test site, enabling robust testing of today's most complex and power-hungry devices. Like the 7038 dual-rack test solution, the 7038 STR will also offer air-cooled thermal management for even more cost-effective test. With asynchronous test capability for up to 48 sites, the system offers a single-vendor turnkey solution that includes socket interface boards (SIBs), sockets, device multi-zone thermal management, software management and control, and an integrated automated handler. This single-source approach eliminates the need to obtain multiple components from different suppliers, streamlining deployment and reducing risk for customers. As device complexity and power requirements continue to rise in the HPC, AI, and automotive markets, the need for advanced SLT and BI solutions has grown significantly. In particular, automotive makers investing heavily in advanced driver assistance systems (ADAS) and telematics processing need a mid-power solution that goes beyond air-cooled thermal solutions for SLT. The 7038 STR provides a solution that can scale with the power and size increase of these processors. Air-cooled systems are limited to approximately 100 W per device, while the 7038 STR's liquid-cooled design supports the higher power levels demanded by next-generation processors with future upgrade capabilities exceeding 1.4 kW. "The 7038 STR represents the next evolution of system-level and burn-in test portfolio. The 7038 STR is especially suited for mid- to low-volume production environments where customers require advanced SLT/BI capabilities without the higher investment and larger footprint of dual-rack systems. Its compatibility with the broader 7038 product family means that customers can easily migrate test programs and hardware between the single- and dual-rack configurations as their production volumes grow. In addition, the system is fully compatible with ATS ActivATE360™?, Advantest's intuitive test management software. ActivATE provides turnkey real-time monitoring, logging, and control across device temperature, current, and power, simplifying program development and ensuring smooth integration into customer test environments. The 7038 Single Test Rack solution is available immediately, with pricing dependent on slot configuration, sites per slot, and thermal requirements. Announcement • Sep 12
Advantest Corporation to Report Q2, 2026 Results on Oct 28, 2025 Advantest Corporation announced that they will report Q2, 2026 results on Oct 28, 2025 Announcement • Sep 09
Advantest Introduces Advanced Mask CD-SEM* E3660 Advantest Corporation announced the release of its next-generation CD-SEM* E3660, engineered for the dimensional metrology of photomasks and EUV masks used in cutting-edge semiconductor manufacturing. Compared to the previous generation's E3650, the E3660 delivers more than a 20% improvement in CD reproducibility, enabling process engineers to meet the stringent requirements of mask manufacturing at the 2nm node and beyond. By reinforcing lithography process control in advanced device fabrication, the E3660 furthers Advantest's vision of providing holistic test solutions across the semiconductor value chain. In semiconductor device fabrication, continuous scaling and pattern complexity are driving a sharp increase in lithographic hotspots--locations where multi-patterning and pattern transfer become particularly error-prone. Masks used to form wafer circuitry are evolving, with higher layer counts and more intricate geometries. This, in turn, has significantly increased the number of required metrology sites, demanding measurement systems with both higher throughput and superior reproducibility. The industry is also transitioning toward curvilinear mask patterns, enabled by advances in multi-beam mask writing and high-performance computing. These patterns are expected to see large-scale deployment around 2027 with the adoption of High Numerical Aperture EUV lithography in device production. To ensure design-to-mask fidelity under these conditions, CD-SEMs must not only provide highly reproducible critical dimension measurements but also generate SEM images with greater fidelity to true pattern contours. Moreover, metrology solutions must evolve to incorporate curvature-sensitive algorithms capable of quantifying deviations between complex mask features and original design intent. Leading up to the development of the E3660, Advantest has collaborated with imec, to validate the correlation of CD-SEM results obtained from the "E3650" with those from Advantest's previous generation CD-SEMs and EDA-based reference data. This enabled Advantest to improve metrology reliability and work with imec to advance the development and validation of new measurement techniques for curvilinear geometries. The E3660 platform reflects the outcome of this collaboration, achieving the reproducibility required for 2nm node mask manufacturing, enabling high-throughput measurement to handle increasing site counts, and providing unique measurement functions for curvilinear patterns. By integrating these capabilities, the E3660 is positioned to deliver robust metrology support for the next generation of mask R&D and production environments. Advantest will initially target the E3660 for deployment at Merchant Mask Shops, where commercial mask manufacturers produce masks for external customers, and Captive Mask Shops, which are in-house mask production facilities of semiconductor manufacturers. This activity establishes the E3660 as a core evaluation tool for advanced mask development and production qualification. Critical Dimension Scanning Electron Microscope: an electron microscope specialized for high-precision measurement of fine pattern dimensions on semiconductor wafers and masks. Announcement • Sep 04
Advantest Corporation to Present Latest Test Solutions At SEMICON Taiwan 2025 Advantest Corporation will present its latest test solutions at SEMICON Taiwan 2025 on Sept. 10-12 at the TaiNEX 1 & 2 in Taipei. At this year's SEMICON Taiwan, Advantest will present innovative, sustainable test technology guided by its new corporate vision, "Be the most trusted and valued test solution company in the semiconductor value chain." Moreover, Advantest's Taiwanese subsidiary will commemorate its 30th anniversary, celebrating decades of service to Taiwan's rapidly growing semiconductor market. Announcement • Aug 04
Advantest Corporation to Showcase Latest Memory Test Solutions At Future of Memory and Storage 2025 Advantest Corporation will showcase its latest memory test systems and solutions at the Future of Memory and Storage 2025 (formerly known as Flash Memory Summit) on Aug. 5-7 at the Santa Clara Convention Center in Santa Clara, California. Advantest is a gold sponsor of the event. Product Highlights: Advantest's booth #634 will be in Hall B of the convention center. The company will feature its end-to-end memory test solutions for testing next-generation memory chips, such as high-bandwidth memory (HBM), DRAM, NAND flash, non-volatile memory (NVM) and protocol storage devices. Advantest will also highlight its new T5801 ultra-high-speed DRAM test system that supports the latest advancements in high-speed memory technologies, including GDDR7, LPDDR6, and DDR6. Announcement • Jun 13
Advantest Corporation to Report Q1, 2026 Results on Jul 29, 2025 Advantest Corporation announced that they will report Q1, 2026 results at 9:00 AM, Tokyo Standard Time on Jul 29, 2025 Announcement • May 12
Advantest Corporation to Showcase Latest Test Solutions At Semicon Southeast Asia 2025 Advantest Corporation will feature its latest test solutions at SEMICON Southeast Asia 2025 on May 20-22 at the Sands Expo and Convention Centre in Singapore. Located in Hall A on Level 1 at Booth #L1511, Advantest will showcase a wide range of solutions that address the technology challenges in the era of complexity. Through this broad product portfolio, Advantest can cater to diverse customer needs, optimizing efficiency to enable critical applications like high-performance computing (HPC), AI, automotive, and 5G/IoT, while supporting crucial technologies such as silicon photonics, high-bandwidth memory (HBM) and 2.5D/3D packaging. Advantest's product highlights will include: NEW SiConic, a scalable solution for automated silicon validation. Designed to address the increasing complexity of advanced systems-on-chip (SoCs), SiConic enables design verification (DV) and silicon validation (SV) engineers to achieve faster sign-off with unparalleled reliability, efficiency and collaboration. Solutions for the V93000 EXA Scale test system, including the Wave Scale RF20ex high-bandwidth RF IC test card, the PMUX02 advanced power multiplexer, the DC Scale XHC32 ultra-high-current power supply card, and the high-speed Pin Scale Multilevel Serial HSIO instrument. Extending the V93000 test system's capabilities to support high-volume production of silicon photonics and co-packaged optics devices via a partnership with FormFactor. The HA1200 die-level handler that can be linked with a tester to utilize Advantest's unique active thermal control technology to test singulated and/or partially assembled dies. ACS Real-Time Data Infrastructure (ACS RTDI™?), a solution platform that automates the process of converting insights into actionable production steps within the same test insertion in milliseconds, optimizing yield, improving quality and reducing time to market. ACS Gemini™? software development platform, which acts as the digital twin to ACS RTDI™? to allow customers to develop, simulate and debug machine learning applications in a virtual environment. NEW Advantest Power Optimization Solution (APOS), a software solution designed to optimize the power management during the V93000 tester's power-on period. It enables foundries and outsourced semiconductor assembly and test (OSAT) providers to achieve their sustainability goals while reducing operational costs. Announcement • May 08
Advantest Corporation Unveils SiConic Test Engineering: Unified, Scalable Bench Environment for Debug and Validation Advantest Corporation unveiled SiConic Test Engineering (TE), the newest addition to the SiConic family introduced in February 2025. SiConic TE offers test engineers the ability to bring up and validate structural and functional tests over high-speed I/O (HSIO) interfaces in a scalable bench environment, enabling earlier validation and debug without occupying valuable ATE systems. SiConic Link flexibly connects to standard evaluation boards through functional interfaces like USB, PCIe, control interfaces, and GPIOs. This is the foundation for SiConic TE to enable test engineers to rapidly validate and debug design verification (DV) and design for test (DFT) content in SiConic's unified environment on the bench. Building on the V93000 test system's leadership in scan over USB or PCIe, SiConic's unified environment brings native DV test content to test engineering without the error-prone and lengthy conversion and debug cycles typical for bring-up of advanced functional tests on ATE. Integrating seamlessly with SiConic Link hardware and the SmarTest 8 software platform, SiConic TE provides users with comprehensive access to functional HSIO links for enhanced throughput and rich trace capabilities during test execution. By enabling smoother handoffs between silicon validation (SV), DV and TE teams, SiConic TE fosters tighter cross-domain collaboration. Through its unified test environment and shared ecosystem, SiConic TE improves the correlation between bench, ATE and SLT systems. The tool's optimized engineering resources allow bring-up and debug to be offloaded from ATE to the bench, freeing up valuable tester capacity and enabling more effective scaling. In addition, tight integration with leading EDA partners enables cross-functional collaboration with leading EDA partners enables Cross-functional collaboration with DV and DFT teams, improving test content development and speeding first-silicon success. Advantest developed SiConic TE in close collaboration with leading customers and EDA partners to ensure seamless integration into existing design and validation flows. Announcement • Mar 18
Advantest Corporation to Showcase Latest IC Test Solutions at SEMICON China 2025, March 26-28 in Shanghai Advantest Corporation will showcase its latest test solutions at SEMICON China 2025 on March 26-28 at the Shanghai New International Expo Centre in Shanghai. Advantest will highlight its broad portfolio of test technology for applications, including advanced memory, automotive, RF wireless communications and CMOS image sensors. Advantest will be located at booth #4431 in Hall N4. This year's digital display will feature key test solutions that enable innovation and technology essential to daily lives, including: NEW T5801 Ultra-High-Speed DRAM test system, engineered to support the latest advancements in high-speed memory technologies, including GDDR7, LPDDR6 and DDR6. NEW solutions for the V93000 EXA Scale test system, including the Wave Scale RF20ex high-bandwidth RF IC test card, the PMUX02 advanced power multiplexer, the DC Scale XHC32 ultra-high-current power supply card, and the high-speed Pin Scale Multilevel Serial HSIO instrument. T2000 SoC test systems with Rapid Development Kit (RDK) for all SoCs, including automotive, power analog and CMOS image sensors. T6391 test system for high-speed, high-accuracy and high-voltage measurement demands to test emerging display driver ICs. ACS TE-Cloud™?, a one-stop test engineering solution platform, offering a complete test development environment with an integrated set of software tools for V93000 test program development. ACS Real-Time Data Infrastructure (ACS RTDI™?), a solution platform that automates the process of converting insights into actionable production steps within the same test insertion in milliseconds, optimizing yield, improving quality and reducing time to market. Announcement • Mar 14
Advantest Corporation to Report Fiscal Year 2025 Results on Apr 25, 2025 Advantest Corporation announced that they will report fiscal year 2025 results on Apr 25, 2025 Announcement • Feb 27
Advantest Corporation to Showcase IC Test Solutions at IESA Vision Summit 2025 Advantest Corporation will showcase its latest test solutions at IESA Vision Summit 2025 on March 5-7 at the Mahatma Mandir, Convention and Exhibition Centre in Gandhinagar, Gujarat, India. Advantest will highlight its broad portfolio of leading-edge test technology for applications, including advanced memory, automotive, artificial intelligence (AI) and high-performance computing (HPC). The IESA Vision Summit is the premier platform dedicated to advancing India's semiconductor and electronics ecosystem, bringing together industry leaders, government policymakers, innovators and experts to discuss cutting-edge technologies, emerging trends and transformative collaborations. As a global leader in providing semiconductor test solutions, Advantest is eager to show its support for India's emerging semiconductor industry. The company is a gold sponsor for this year's event. Product Displays: Advantest will be located at booth #212 in Hall 1. This year's digital display will feature key test solutions that enable innovation and technology essential to daily lives, including: NEW SiConic, a scalable solution for automated silicon validation. Designed to address the increasing complexity of advanced systems-on-chip (SoCs), SiConic enables design verification (DV) and silicon validation (SV) engineers to achieve faster sign-off with unparalleled reliability, efficiency and collaboration. NEW solutions for the V93000 EXA Scale test system, including the Wave Scale RF20ex high-bandwidth RFIC test card, the DC Scale XHC32 ultra-high-current power supply card and the high-speed Pin Scale Multilevel Serial HSIO instrument. NEW T5801 Ultra-High-Speed DRAM test system, engineered to support the latest advancements in high-speed memory technologies - including GDDR7, LPDDR6 and DDR6 - critical to meeting the growing demands of artificial intelligence (AI), high-performance computing (H PC) and edge applications. Instruments for the V93000EXA Scale test system that enable the testing of power and analog devices, such as battery management systems (BMS), automotive and power ICs, including the new PMUX02 advanced power multiplexer and the Pin Scale 5000 digital card. Announcement • Feb 20
Advantest Introduces Siconic: Groundbreaking Solution for Automated Silicon Validation Advantest Corporation unveiled SiConic: a scalable solution for automated silicon validation. Designed to address the increasing complexity of advanced systems-on-chip (SoCs), SiConic enables design verification (DV) and silicon validation (SV) engineers to achieve faster sign-off with unparalleled reliability, efficiency and collaboration. Debuting next week at DVCon in San Jose, Calif., SiConic signals Advantest’s commitment to transforming the R&D process for its customers. The semiconductor industry is facing unprecedented challenges. Growing SoC design complexity, together with the adoption of 3D packaging and heterogeneous integration, is straining traditional validation workflows. DV and SV teams are under pressure to reduce time-to-market and time-to-quality – even as more devices with more intricate features are being developed within constrictive timelines. Reusing the wealth of verification content developed in pre-silicon would provide an efficiency and quality breakthrough. However, the industry lacks the automated flow and tools to reliably re-use and extend verification tests for silicon validation. SiConic’s ecosystem – including EDA partners such as Cadence, Siemens and Synopsys – overcomes this barrier to reuse, enabling engineering efficiency and accelerated test execution on real silicon. SiConic Explorer, the platform’s software backbone, offers an automated flow by integrating seamlessly with EDA verification tools based on the Accellera Portable Test and Stimulus Standard (PSS), e.g., the Cadence Perspec System Verifier. In addition, integration with debuggers, such as Lauterbach’s TRACE32 debugging tool, accelerates the bring-up of complex multi-IP test cases. SiConic Link is the hardware foundation of the SiConic solution on a bench. With its high-speed I/O (HSIO) capability, SiConic Link supports protocols such as PCIe and USB to enable functional validation with high throughput and rich tracing capabilities during test execution. The test instrument provides control interfaces (e.g., JTAG, SPI) and general-purpose I/Os, improves the debugging workflow and provides extensive control and observability of the device in its target board environment. With SiConic, DV engineers can now leverage familiar pre-silicon techniques, expanding their functional coverage in post-silicon. Similarly, SV engineers benefit from seamless load, set parameters and debug of PSS-based or manually directed content on silicon, thereby enabling rapid and reliable device bring-up and functional characterization. The highly portable solution can be easily scaled for use by distributed global R&D teams collaborating on a complex SoC with diverse IP blocks. SiConic enables confident sign-off decisions through team collaboration and data-driven insights – building trust with customers receiving early samples and expecting reliable ramp and operation during the lifetime of their systems. Leading Advantest IC customers and EDA partners are already working with SiConic and seeing the benefits of its performance and productivity advantages. 
