Announcement • Aug 14

TIER IV Joins JST Next-Generation Edge Ai Semiconductor R&D Program to Open-Source Ai Chip Designs for Autonomous Driving

TIER IV, the pioneering force behind open-source software for autonomous driving, has joined the Next-Generation Edge AI Semiconductor Research and Development Program led by the Japan Science and Technology Agency (JST) to advance research and development of a software-defined system-on-chip (SoC) for Level 4 autonomous driving. Under the JST program, a research team led by Professor Yoshihiro Kawahara of Graduate School of Engineering, The University of Tokyo, will advance research into use-case-driven, functionally differentiated physical AI chip design. Meanwhile, TIER IV is developing the logic design of an AI chip designed to efficiently process inference for end-to-end (E2E) autonomous driving AI, with the goal of open-sourcing the design assets and associated toolchain. Through this initiative, TIER IV will independently design an AI chip for autonomous driving that supports Autoware, the world's leading open-source software for autonomous driving, and evaluate its effectiveness as part of an SoC. In addition to the chip's logic design, TIER IV will open-source the compiler and related toolchain. By making these technologies available, TIER IV aims to establish an open ecosystem in which semiconductor manufacturers can leverage its platform technologies to accelerate the commercialization of SoCs for Level 4 autonomous driving. Autonomous driving AI increasingly relies on large-scale Transformer models that process sensor inputs, such as camera images and point cloud data, in an integrated manner from perception through motion planning. This initiative will focus on Transformer inference and develop a dedicated architecture that simplifies the complex control mechanisms required for general-purpose computing. Data required for AI model execution will be efficiently placed in advance and repeatedly reused within the chip, reducing the power consumed by external memory transfers and computation control. The architecture will also incorporate dedicated compute circuits for operations frequently used in Transformers, including matrix multiplication and attention mechanisms. Rather than optimizing only the chip's peak performance, TIER IV will seek to improve performance per watt across the entire autonomous driving system, including Autoware. The design will support flexible deployment across a broad range of applications, from embedded devices operating at several watts to in-vehicle electronic control units operating at several tens of watts. The technology landscape surrounding autonomous driving AI is evolving rapidly, making it difficult for architectures designed around a specific model or hardware configuration to adapt continuously to change. To address this challenge, TIER IV will introduce the Tensor Operator Set Architecture (TOSA), a standardized intermediate representation, between AI models and the AI chip. Operations from AI models developed in frameworks such as PyTorch will be converted into a common TOSA representation. Optimization and code generation will then be performed through TOSA before execution on the AI chip, enabling loose coupling between AI frameworks and hardware. As a result, changes in AI model architectures or computational methods can be accommodated primarily through software updates to components such as the compiler and runtime, without requiring the entire chip to be redesigned from scratch. TIER IV aims to realize a software-defined SoC whose performance and power efficiency can be continuously optimized through software. In safety-critical applications such as Level 4 autonomous driving, it is important to understand not only the AI model itself, but also the internal architecture and processing flow of the computing system on which it runs. Under this initiative, TIER IV will open-source the logic design of its autonomous driving AI chip, together with the compiler and related toolchain. By making the design information publicly available, TIER IV will enable semiconductor manufacturers and developers to inspect the chip's internal architecture and software behavior, and to modify, extend, and reuse the technologies according to their vehicle platforms, AI models, performance requirements, and power constraints. Just as Autoware has enabled collaborative development of autonomous driving software, TIER IV will extend the same open-source philosophy to AI chip design and related toolchains. This will support an ecosystem in which autonomous driving AI technologies can be continuously improved and advanced without dependence on specific semiconductor products or closed development environments. The process of executing an AI model on a chip involves model-format conversion, computational optimization, quantization, rounding, and other transformations. These processes are essential to improving performance and power efficiency, but they may also introduce numerical differences that affect the final computation results. A mechanism is therefore needed to assess the impact of such differences. Using TOSA and its clearly defined operator specifications as a foundation, TIER IV will structure the compilation transformation process and introduce formal verification techniques. For selected transformations and operations, the initiative will establish mechanisms to mathematically verify numerical consistency before and after transformation, as well as compliance with predefined error tolerances. Through this approach, TIER IV will pursue not only high processing performance, but also an execution environment in which the transformations applied to an AI model before chip execution can be traced and the correctness of the resulting processing can be verified. This will contribute to a more reliable execution environment for autonomous driving AI.

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