View Financial HealthSynopsys 배당 및 자사주 매입배당 기준 점검 0/6Synopsys 배당금을 지급한 기록이 없습니다.핵심 정보n/a배당 수익률-2.2%자사주 매입 수익률총 주주 수익률-2.2%미래 배당 수익률0%배당 성장률n/a다음 배당 지급일n/a배당락일n/a주당 배당금n/a배당 성향n/a최근 배당 및 자사주 매입 업데이트업데이트 없음모든 업데이트 보기Recent updates공고 • 1hSynopsys, Inc. to Report Q3, 2026 Results on Aug 26, 2026Synopsys, Inc. announced that they will report Q3, 2026 results on Aug 26, 2026공고 • Jun 29+ 6 more updatesSynopsys, Inc.(NasdaqGS:SNPS) dropped from Russell 1000 Growth BenchmarkSynopsys, Inc.(NasdaqGS:SNPS) dropped from Russell 1000 Growth Benchmark공고 • Jun 19Synopsys Announces Availability of the First Wave of Multiphysics Fusion SolutionsSynopsys, Inc. announced availability of its first Multiphysics Fusion solutions for customer deployment. The Multiphysics Fusion portfolio combines Synopsys' AI-powered EDA solutions with Ansys golden signoff analysis across timing signoff, design closure, multi-die design, and analog workflows. The first Multiphysics Fusion solutions include targeted GPU-accelerated flows powered by NVIDIA CUDA-X libraries such as cuDSS. Multiphysics Fusion for Timing Signoff enables up to 3x faster runtimes, SPICE-accurate multiphysics timing analysis. Integrates Synopsys PrimeTime with RedHawk-SC and RedHawk-SC Electrothermal, along with unified full-spectrum RC extraction using Synopsys StarRC and multiphysics HFSS-IC, to incorporate IR, thermal, and stress effects, improving margins and reducing IR-induced timing escapes. Multiphysics Fusion for Design Closure delivers up to 10x faster design closure with higher engineering change order (ECO) success rates and improved power, performance and area (PPA). Combines Synopsys PrimeClosure with RedHawk-SC to embed power integrity into golden signoff optimization, accelerating convergence with fewer iterations. Multiphysics Fusion for Multi-die Designs provides unified Synopsys 3DIC Compiler platform with RedHawk-SC, RedHawk-SC Electrothermal and multiphysics HFSS-IC for concurrent power integrity, thermal, and electromagnetic analysis, providing early system insights from exploration to golden signoff with correct-by-construction design. Multiphysics Fusion for Analog & Photonic Design integrates Synopsys Custom Compiler with multiphysics HFSS-IC for on-chip, high accuracy electromagnetic analysis into the analog design flow, and Synopsys OptoCompiler with Lumerical enabling end-to-end photonic IC and co-packaged optics systems. Early engagements with semiconductor and systems companies validate the value of Multiphysics Fusion solutions. Synopsys Multiphysics Fusion solutions enable up to 5x faster design closure and up to 86% IR fix rates in selected pilot designs. Synopsys' Multiphysics Fusion technology provides a unified, all-aware timing signoff platform by integrating PrimeTime with multiphysics insight, delivering SPICE-accurate correlation and enabling margin recovery. The Cisco Silicon One group is leveraging Synopsys Multiphysics Fusion technology to unify IR drop effects within signoff design closure to gain earlier, more accurate visibility into real-world conditions. Combined with signoff-accurate, timing-aware IR fixing, this enables predictive optimization—helping Cisco Silicon One converge on power integrity issues faster, deliver better PPA, and achieve significantly faster runtime. Multiphysics Fusion solutions for timing signoff, design closure, multi-die design, and analog and photonic design are available.공고 • Jun 04GlobalFoundries Inc. (NasdaqGS:GFS) completed the acquisition of Processor IP Solutions Business of Synopsys, Inc. (NasdaqGS:SNPS).GlobalFoundries Inc. (NasdaqGS:GFS) entered into a definitive agreement to acquire Processor IP Solutions Business of Synopsys, Inc. (NasdaqGS:SNPS) on January 14, 2026. GF is acquiring the Synopsys Processor IP portfolio, which consists of ARC-V™ (RISC-V) and ARC® CPU IP, DSP IP, Neural Network Processing Unit (NPU) IP, and related software development tools, including ARC MetaWare Development Toolkits. The transaction also includes Synopsys' ASIP Designer™ and ASIP Programmer™ tools for automating the design and implementation of application-specific instruction-set processors (ASIPs). The transaction is expected to be completed in the second half of calendar year 2026, subject to the satisfaction of customary closing conditions, including the receipt of required regulatory approvals. GlobalFoundries Inc. (NasdaqGS:GFS) completed the acquisition of Processor IP Solutions Business of Synopsys, Inc. (NasdaqGS:SNPS) on June 2, 2026.공고 • May 28+ 1 more updateSynopsys Inc. Appoints Jesse Cohn as Independent Director, Effective June 1, 2026Synopsys Inc. announced it has entered into a cooperation agreement with Elliott Investment Management L.P., including the appointment of Jesse Cohn to its board of directors as an independent director, effective June 1, 2026. Cohn is a Managing Partner at Elliott with a long track record of success as an investor in and director of public technology companies. With Cohn joining, the Synopsys Board of Directors expands to 11 members. Under the cooperation agreement, Elliott has agreed to customary standstill, voting, and confidentiality commitments, among other provisions. Cohn also will join the Corporate Governance and Nominating Committee of the Board. Jesse Cohn is a Managing Partner and member of the Management, Risk, Allocation and Investment Committees at Elliott. He has served as an independent director of several public technology companies including Citrix Systems, eBay, and Twitter and is a member of the advisory board at the Harvard Law School Program on Corporate Governance. Prior to joining Elliott in 2004, Cohn was an Analyst in the mergers and acquisitions group at Morgan Stanley. He earned his B.S. in Economics from the University of Pennsylvania'sWharton School of Business, from which he graduated summa cum laude.공고 • Apr 28Synopsys, Inc. to Report Q2, 2026 Results on May 27, 2026Synopsys, Inc. announced that they will report Q2, 2026 results at 4:00 PM, US Eastern Standard Time on May 27, 2026공고 • Apr 08Ultra Accelerator Link Consortium Publishes Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G PerformanceUltra Accelerator Link Consortium, the industry standards organization developing the open scale-up interconnect for next-generation AI workloads, announced the ratification of the next UALink Specification, which encompasses three major additions – In-Network Compute, Chiplet Definition, and Manageability. The new specifications support the deployment of UALink solutions in multi-workload environments, while simultaneously helping improve UALink technology efficiency, performance for AI workloads and ease of implementation. The UALink Consortium provides a standardized foundation for accelerator connectivity at scale, helping drive innovation, increase deployment flexibility and support the rapidly growing performance demands of next-generation AI workloads. The new specification update is facilitated through UALink Consortium’s open governance model, which fosters innovation while enabling a robust, multi-vendor supply chain, providing system designers and cloud providers with the necessary flexibility to deploy interoperable solutions without vendor lock-in. New UALink Specifications: UALink Common Specification 2.0 introduces In-Network Compute for UALink technology, facilitating computation and communication between accelerators. Reduces latency, saves bandwidth, and improves scaling efficiency for distributed training and inference for AI solutions for complex and multi-workload environments for UALink systems. UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0 split the DL/PL Specification from the UALink Common Specification to enable UALink to move quickly as new physical layers and speeds are needed by the industry without requiring changes to the other specifications. UALink Manageability Specification 1.0 introduces UALink as a system with centralized control and management planes. Utilizes standardized protocols, modeling and APIs like gNMI, Yang, SAI and Redfish. UALink Chiplet Specification 1.0 defines the necessary information to integrate UALink technology into chiplet-based SoCs, including interfaces, form factors, flow control and chiplet management standardization. Fully compliant with the UCIe 3.0 Specification for simplified integration into existing chiplet ecosystems. All of the UALink specifications are available for public download.공고 • Mar 30Synopsys, Inc. announced that it has received funding from Elliott Investment Management L.P.Synopsys, Inc announced a private placement to issue several billion dollars on March 28, 2026. The transaction included participation from new investor Elliott Investment Management L.P and issued common shares.공고 • Mar 12+ 1 more updateSynopsys Introduces Software-Defined Hardware-Assisted Verification to Enable Ai ProliferationSynopsys, Inc. announced advancements across its leading hardware-assisted verification (HAV) portfolio, including new hardware platforms and capabilities to support the ever-expanding demand for AI chip verification from the data center to the edge. Synopsys HAV platforms, powered by the company's unique software-defined capabilities, set new performance, scalability, and use case benchmarks for verifying the world's most sophisticated multi-die and AI chips amidst compounding design complexity and time-to-market requirements. AI chip verification complexity is escalating rapidly as large language models continue to double in size roughly every four months, and interface data rates advance at a 2x rate every three years. Simultaneously, edge AI architectures are driving aggressive throughput, latency, and power-efficiency targets that further expand the design and validation workload. To keep pace, the industry requires HAV solutions to support broader application coverage and run quadrillions of verification cycles, enabling first-time-right silicon and a seamless ability to integrate heterogeneous AI systems. The latest advancements across Synopsys' software-defined hardware-assisted verification portfolio, include: Breakthrough performance and capacity for the AI era: The latest software-defined updates and modular HAV are available across the ZeBu and HAPS platforms. Of note, with these updates, the industry's highest capacity-scalable emulation platform, ZeBu Server 5, supports complex designs to meet the demands of mega designs supporting data center AI training and inference, GPU, custom accelerators, and networking IPU/DPU workloads. Modular HAV for HAPS enables the largest prototypes for software development, with further improvements for compute, storage, and bring-up capabilities. New HAPS and ZeBu platforms: The new HAPS-200 12 FPGA and ZeBu-200 12 FPGA systems address the complexity and high-performance requirements for data center-sub-system, mobile, client, server, consumer, and edge AI applications. They deliver 2x higher capacity compared to previous 6 FPGA platforms utilizing the flagship AMD Versal™ Premium VP1902 adaptive SoCs, offering EP-Ready Hardware-enabled configurability between prototyping and emulation. Synopsys also introduces the new HAPS-200 1 FPGA platform as a desktop system ideal for IP verification and software bring-up using Synopsys Interface Prototyping Kits. Software-defined HAV capabilities extend system lifetime value: Continuous software improvements deliver compounding performance gains, increased debug productivity, as well as additional use case capabilities for both new and installed systems. The Synopsys HAV portfolio supports new, industry-first Hardware-Assisted Test Solutions, test automation capabilities that allow teams to stress corner cases for processor, memory, and I/O subsystems as well as full-system coherency validation and observe system behavior under realistic workloads in emulation long before silicon is ready. For mixed-signal and system-level designs, Real-Number Models (RNM) emulation enables fast, scalable abstraction of analog behavior within digital-centric verification flows for faster software bring-up. For safety-critical and high-reliability designs, new fault emulation capabilities enable scalable fault injection and analysis across RTL simulation, emulation, and prototyping.공고 • Mar 10Synopsys Launches Electronics Digital Twin Platform For Physical AI System DevelopmentSynopsys, Inc. launched the Synopsys Electronics Digital Twin (eDT) Platform, a first-of-its-kind, open solution to accelerate the creation, management, deployment, and use of electronics digital twins (eDTs) critical for software-defined product development enabling physical AI systems. The platform enables users to configure cloud-based eDT Labs, a collection of pre-integrated assets including Synopsys technologies, open-ecosystem tools, models, software, and scalable compute for high-value automotive use cases. The eDT Platform includes Synopsys and partner capabilities that can be used to establish eDT Labs such as Synopsys' virtualization and AI technologies, advanced debug, test tools, ecosystem integration, and blueprints to rapidly build and validate eDTs. System composition uses the open-source SIL Kit by Vector and Synopsys, enabling teams to rapidly assemble and connect virtual ECUs, models, and software components. A broad set of pre-integrated ecosystem partner technologies including silicon models; simulation, debug and analysis tools; and software IP; among others. eDT Labs can be deployed and managed easily using platform capabilities, including provisioning, role-based user management, secure access and encryption, administrative analytics, global license provisioning, and a workflow editor. User interfaces, applications, and APIs (CLI and TEST APIs) integrate with commercial and customer software factory solutions. Flexible compute options with SaaS or BYOC deployment options leverage flexible compute in the cloud, powered by AWS cloud infrastructure and AWS Graviton4 processors delivering computational performance and flexibility required for modern automotive development. The platform enables OEMs to achieve up to 90% of software validation prior to hardware availability by shifting software development and system integration "left," reducing vehicle development cost and time-to-market. The platform enables seamless collaboration between customer teams, suppliers and tool vendors to accelerate time to market. Integration in continuous integration/testing workflows with rapid provisioning of eDTs reduces validation effort while improving software quality.지급의 안정성과 성장배당 데이터 가져오는 중안정적인 배당: 과거에 SYNP03 의 주당 배당금이 안정적이었는지 판단하기에는 데이터가 부족합니다.배당금 증가: SYNP03 의 배당금 지급이 증가했는지 판단하기에는 데이터가 부족합니다.배당 수익률 vs 시장Synopsys 배당 수익률 vs 시장SYNP03의 배당 수익률은 시장과 어떻게 비교되나요?구분배당 수익률회사 (SYNP03)n/a시장 하위 25% (TH)3.1%시장 상위 25% (TH)7.2%업계 평균 (Software)1.2%분석가 예측 (SYNP03) (최대 3년)0%주목할만한 배당금: 회사가 최근 지급을 보고하지 않았기 때문에 하위 25%의 배당금 지급자에 대해 SYNP03 의 배당 수익률을 평가할 수 없습니다.고배당: 회사가 최근 지급을 보고하지 않았기 때문에 배당금 지급자의 상위 25%에 대해 SYNP03 의 배당 수익률을 평가할 수 없습니다.주주 대상 이익 배당수익 보장: 배당금 지급이 수익으로 충당되는지 확인하기 위해 SYNP03 의 지급 비율을 계산하기에는 데이터가 부족합니다.주주 현금 배당현금 흐름 범위: SYNP03 에서 지급을 보고하지 않았기 때문에 배당 지속 가능성을 계산할 수 없습니다.높은 배당을 제공하는 우량 기업 찾기7D1Y7D1Y7D1YTH 시장에서 배당이 강한 기업.View Management기업 분석 및 재무 데이터 상태데이터최종 업데이트 (UTC 시간)기업 분석2026/07/22 04:28종가2026/07/22 00:00수익2026/04/30연간 수익2025/10/31데이터 소스당사의 기업 분석에 사용되는 데이터는 S&P Global Market Intelligence LLC에서 제공됩니다. 아래 데이터는 이 보고서를 생성하기 위해 분석 모델에서 사용됩니다. 데이터는 정규화되므로 소스가 제공된 후 지연이 발생할 수 있습니다.패키지데이터기간미국 소스 예시 *기업 재무제표10년손익계산서현금흐름표대차대조표SEC 양식 10-KSEC 양식 10-Q분석가 컨센서스 추정치+3년재무 예측분석가 목표주가분석가 리서치 보고서Blue Matrix시장 가격30년주가배당, 분할 및 기타 조치ICE 시장 데이터SEC 양식 S-1지분 구조10년주요 주주내부자 거래SEC 양식 4SEC 양식 13D경영진10년리더십 팀이사회SEC 양식 10-KSEC 양식 DEF 14A주요 개발10년회사 공시SEC 양식 8-K* 미국 증권에 대한 예시이며, 비(非)미국 증권에는 해당 국가의 규제 서식 및 자료원을 사용합니다.별도로 명시되지 않는 한 모든 재무 데이터는 연간 기간을 기준으로 하지만 분기별로 업데이트됩니다. 이를 TTM(최근 12개월) 또는 LTM(지난 12개월) 데이터라고 합니다. 자세히 알아보기.분석 모델 및 스노우플레이크이 보고서를 생성하는 데 사용된 분석 모델의 세부 정보는 당사의 GitHub 페이지에서 확인하실 수 있습니다. 또한 보고서 사용 방법에 대한 가이드와 YouTube 튜토리얼도 제공하고 있습니다.Simply Wall St 분석 모델을 설계하고 구축한 세계적 수준의 팀에 대해 알아보세요.산업 및 섹터 지표산업 및 섹터 지표는 Simply Wall St가 6시간마다 계산하며, 프로세스에 대한 자세한 내용은 Github에서 확인할 수 있습니다.분석가 소스Synopsys, Inc.는 33명의 분석가가 다루고 있습니다. 이 중 24명의 분석가가 우리 보고서에 입력 데이터로 사용되는 매출 또는 수익 추정치를 제출했습니다. 분석가의 제출 자료는 하루 종일 업데이트됩니다.분석가기관Joseph VruwinkBairdGary MobleyBenchmark CompanyNay Soe NaingBerenberg30명의 분석가 더 보기
공고 • 1hSynopsys, Inc. to Report Q3, 2026 Results on Aug 26, 2026Synopsys, Inc. announced that they will report Q3, 2026 results on Aug 26, 2026
공고 • Jun 29+ 6 more updatesSynopsys, Inc.(NasdaqGS:SNPS) dropped from Russell 1000 Growth BenchmarkSynopsys, Inc.(NasdaqGS:SNPS) dropped from Russell 1000 Growth Benchmark
공고 • Jun 19Synopsys Announces Availability of the First Wave of Multiphysics Fusion SolutionsSynopsys, Inc. announced availability of its first Multiphysics Fusion solutions for customer deployment. The Multiphysics Fusion portfolio combines Synopsys' AI-powered EDA solutions with Ansys golden signoff analysis across timing signoff, design closure, multi-die design, and analog workflows. The first Multiphysics Fusion solutions include targeted GPU-accelerated flows powered by NVIDIA CUDA-X libraries such as cuDSS. Multiphysics Fusion for Timing Signoff enables up to 3x faster runtimes, SPICE-accurate multiphysics timing analysis. Integrates Synopsys PrimeTime with RedHawk-SC and RedHawk-SC Electrothermal, along with unified full-spectrum RC extraction using Synopsys StarRC and multiphysics HFSS-IC, to incorporate IR, thermal, and stress effects, improving margins and reducing IR-induced timing escapes. Multiphysics Fusion for Design Closure delivers up to 10x faster design closure with higher engineering change order (ECO) success rates and improved power, performance and area (PPA). Combines Synopsys PrimeClosure with RedHawk-SC to embed power integrity into golden signoff optimization, accelerating convergence with fewer iterations. Multiphysics Fusion for Multi-die Designs provides unified Synopsys 3DIC Compiler platform with RedHawk-SC, RedHawk-SC Electrothermal and multiphysics HFSS-IC for concurrent power integrity, thermal, and electromagnetic analysis, providing early system insights from exploration to golden signoff with correct-by-construction design. Multiphysics Fusion for Analog & Photonic Design integrates Synopsys Custom Compiler with multiphysics HFSS-IC for on-chip, high accuracy electromagnetic analysis into the analog design flow, and Synopsys OptoCompiler with Lumerical enabling end-to-end photonic IC and co-packaged optics systems. Early engagements with semiconductor and systems companies validate the value of Multiphysics Fusion solutions. Synopsys Multiphysics Fusion solutions enable up to 5x faster design closure and up to 86% IR fix rates in selected pilot designs. Synopsys' Multiphysics Fusion technology provides a unified, all-aware timing signoff platform by integrating PrimeTime with multiphysics insight, delivering SPICE-accurate correlation and enabling margin recovery. The Cisco Silicon One group is leveraging Synopsys Multiphysics Fusion technology to unify IR drop effects within signoff design closure to gain earlier, more accurate visibility into real-world conditions. Combined with signoff-accurate, timing-aware IR fixing, this enables predictive optimization—helping Cisco Silicon One converge on power integrity issues faster, deliver better PPA, and achieve significantly faster runtime. Multiphysics Fusion solutions for timing signoff, design closure, multi-die design, and analog and photonic design are available.
공고 • Jun 04GlobalFoundries Inc. (NasdaqGS:GFS) completed the acquisition of Processor IP Solutions Business of Synopsys, Inc. (NasdaqGS:SNPS).GlobalFoundries Inc. (NasdaqGS:GFS) entered into a definitive agreement to acquire Processor IP Solutions Business of Synopsys, Inc. (NasdaqGS:SNPS) on January 14, 2026. GF is acquiring the Synopsys Processor IP portfolio, which consists of ARC-V™ (RISC-V) and ARC® CPU IP, DSP IP, Neural Network Processing Unit (NPU) IP, and related software development tools, including ARC MetaWare Development Toolkits. The transaction also includes Synopsys' ASIP Designer™ and ASIP Programmer™ tools for automating the design and implementation of application-specific instruction-set processors (ASIPs). The transaction is expected to be completed in the second half of calendar year 2026, subject to the satisfaction of customary closing conditions, including the receipt of required regulatory approvals. GlobalFoundries Inc. (NasdaqGS:GFS) completed the acquisition of Processor IP Solutions Business of Synopsys, Inc. (NasdaqGS:SNPS) on June 2, 2026.
공고 • May 28+ 1 more updateSynopsys Inc. Appoints Jesse Cohn as Independent Director, Effective June 1, 2026Synopsys Inc. announced it has entered into a cooperation agreement with Elliott Investment Management L.P., including the appointment of Jesse Cohn to its board of directors as an independent director, effective June 1, 2026. Cohn is a Managing Partner at Elliott with a long track record of success as an investor in and director of public technology companies. With Cohn joining, the Synopsys Board of Directors expands to 11 members. Under the cooperation agreement, Elliott has agreed to customary standstill, voting, and confidentiality commitments, among other provisions. Cohn also will join the Corporate Governance and Nominating Committee of the Board. Jesse Cohn is a Managing Partner and member of the Management, Risk, Allocation and Investment Committees at Elliott. He has served as an independent director of several public technology companies including Citrix Systems, eBay, and Twitter and is a member of the advisory board at the Harvard Law School Program on Corporate Governance. Prior to joining Elliott in 2004, Cohn was an Analyst in the mergers and acquisitions group at Morgan Stanley. He earned his B.S. in Economics from the University of Pennsylvania'sWharton School of Business, from which he graduated summa cum laude.
공고 • Apr 28Synopsys, Inc. to Report Q2, 2026 Results on May 27, 2026Synopsys, Inc. announced that they will report Q2, 2026 results at 4:00 PM, US Eastern Standard Time on May 27, 2026
공고 • Apr 08Ultra Accelerator Link Consortium Publishes Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G PerformanceUltra Accelerator Link Consortium, the industry standards organization developing the open scale-up interconnect for next-generation AI workloads, announced the ratification of the next UALink Specification, which encompasses three major additions – In-Network Compute, Chiplet Definition, and Manageability. The new specifications support the deployment of UALink solutions in multi-workload environments, while simultaneously helping improve UALink technology efficiency, performance for AI workloads and ease of implementation. The UALink Consortium provides a standardized foundation for accelerator connectivity at scale, helping drive innovation, increase deployment flexibility and support the rapidly growing performance demands of next-generation AI workloads. The new specification update is facilitated through UALink Consortium’s open governance model, which fosters innovation while enabling a robust, multi-vendor supply chain, providing system designers and cloud providers with the necessary flexibility to deploy interoperable solutions without vendor lock-in. New UALink Specifications: UALink Common Specification 2.0 introduces In-Network Compute for UALink technology, facilitating computation and communication between accelerators. Reduces latency, saves bandwidth, and improves scaling efficiency for distributed training and inference for AI solutions for complex and multi-workload environments for UALink systems. UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0 split the DL/PL Specification from the UALink Common Specification to enable UALink to move quickly as new physical layers and speeds are needed by the industry without requiring changes to the other specifications. UALink Manageability Specification 1.0 introduces UALink as a system with centralized control and management planes. Utilizes standardized protocols, modeling and APIs like gNMI, Yang, SAI and Redfish. UALink Chiplet Specification 1.0 defines the necessary information to integrate UALink technology into chiplet-based SoCs, including interfaces, form factors, flow control and chiplet management standardization. Fully compliant with the UCIe 3.0 Specification for simplified integration into existing chiplet ecosystems. All of the UALink specifications are available for public download.
공고 • Mar 30Synopsys, Inc. announced that it has received funding from Elliott Investment Management L.P.Synopsys, Inc announced a private placement to issue several billion dollars on March 28, 2026. The transaction included participation from new investor Elliott Investment Management L.P and issued common shares.
공고 • Mar 12+ 1 more updateSynopsys Introduces Software-Defined Hardware-Assisted Verification to Enable Ai ProliferationSynopsys, Inc. announced advancements across its leading hardware-assisted verification (HAV) portfolio, including new hardware platforms and capabilities to support the ever-expanding demand for AI chip verification from the data center to the edge. Synopsys HAV platforms, powered by the company's unique software-defined capabilities, set new performance, scalability, and use case benchmarks for verifying the world's most sophisticated multi-die and AI chips amidst compounding design complexity and time-to-market requirements. AI chip verification complexity is escalating rapidly as large language models continue to double in size roughly every four months, and interface data rates advance at a 2x rate every three years. Simultaneously, edge AI architectures are driving aggressive throughput, latency, and power-efficiency targets that further expand the design and validation workload. To keep pace, the industry requires HAV solutions to support broader application coverage and run quadrillions of verification cycles, enabling first-time-right silicon and a seamless ability to integrate heterogeneous AI systems. The latest advancements across Synopsys' software-defined hardware-assisted verification portfolio, include: Breakthrough performance and capacity for the AI era: The latest software-defined updates and modular HAV are available across the ZeBu and HAPS platforms. Of note, with these updates, the industry's highest capacity-scalable emulation platform, ZeBu Server 5, supports complex designs to meet the demands of mega designs supporting data center AI training and inference, GPU, custom accelerators, and networking IPU/DPU workloads. Modular HAV for HAPS enables the largest prototypes for software development, with further improvements for compute, storage, and bring-up capabilities. New HAPS and ZeBu platforms: The new HAPS-200 12 FPGA and ZeBu-200 12 FPGA systems address the complexity and high-performance requirements for data center-sub-system, mobile, client, server, consumer, and edge AI applications. They deliver 2x higher capacity compared to previous 6 FPGA platforms utilizing the flagship AMD Versal™ Premium VP1902 adaptive SoCs, offering EP-Ready Hardware-enabled configurability between prototyping and emulation. Synopsys also introduces the new HAPS-200 1 FPGA platform as a desktop system ideal for IP verification and software bring-up using Synopsys Interface Prototyping Kits. Software-defined HAV capabilities extend system lifetime value: Continuous software improvements deliver compounding performance gains, increased debug productivity, as well as additional use case capabilities for both new and installed systems. The Synopsys HAV portfolio supports new, industry-first Hardware-Assisted Test Solutions, test automation capabilities that allow teams to stress corner cases for processor, memory, and I/O subsystems as well as full-system coherency validation and observe system behavior under realistic workloads in emulation long before silicon is ready. For mixed-signal and system-level designs, Real-Number Models (RNM) emulation enables fast, scalable abstraction of analog behavior within digital-centric verification flows for faster software bring-up. For safety-critical and high-reliability designs, new fault emulation capabilities enable scalable fault injection and analysis across RTL simulation, emulation, and prototyping.
공고 • Mar 10Synopsys Launches Electronics Digital Twin Platform For Physical AI System DevelopmentSynopsys, Inc. launched the Synopsys Electronics Digital Twin (eDT) Platform, a first-of-its-kind, open solution to accelerate the creation, management, deployment, and use of electronics digital twins (eDTs) critical for software-defined product development enabling physical AI systems. The platform enables users to configure cloud-based eDT Labs, a collection of pre-integrated assets including Synopsys technologies, open-ecosystem tools, models, software, and scalable compute for high-value automotive use cases. The eDT Platform includes Synopsys and partner capabilities that can be used to establish eDT Labs such as Synopsys' virtualization and AI technologies, advanced debug, test tools, ecosystem integration, and blueprints to rapidly build and validate eDTs. System composition uses the open-source SIL Kit by Vector and Synopsys, enabling teams to rapidly assemble and connect virtual ECUs, models, and software components. A broad set of pre-integrated ecosystem partner technologies including silicon models; simulation, debug and analysis tools; and software IP; among others. eDT Labs can be deployed and managed easily using platform capabilities, including provisioning, role-based user management, secure access and encryption, administrative analytics, global license provisioning, and a workflow editor. User interfaces, applications, and APIs (CLI and TEST APIs) integrate with commercial and customer software factory solutions. Flexible compute options with SaaS or BYOC deployment options leverage flexible compute in the cloud, powered by AWS cloud infrastructure and AWS Graviton4 processors delivering computational performance and flexibility required for modern automotive development. The platform enables OEMs to achieve up to 90% of software validation prior to hardware availability by shifting software development and system integration "left," reducing vehicle development cost and time-to-market. The platform enables seamless collaboration between customer teams, suppliers and tool vendors to accelerate time to market. Integration in continuous integration/testing workflows with rapid provisioning of eDTs reduces validation effort while improving software quality.