View ValuationAndes Technology 향후 성장Future 기준 점검 5/6Andes Technology은 연간 수입과 매출이 각각 132%와 28.2% 증가할 것으로 예상되고 EPS는 연간 132%만큼 증가할 것으로 예상됩니다.핵심 정보132.0%이익 성장률132.01%EPS 성장률Semiconductor 이익 성장0%매출 성장률28.2%향후 자기자본이익률n/a애널리스트 커버리지Low마지막 업데이트14 Apr 2026최근 향후 성장 업데이트업데이트 없음모든 업데이트 보기Recent updates공시 • Mar 10Andes Technology Corporation, Annual General Meeting, May 28, 2026Andes Technology Corporation, Annual General Meeting, May 28, 2026, at 10:00 Taipei Standard Time. Location: 4 floor no,1, kung yeh tung 2nd rd., hsinchu science park, hsinchu city Taiwan공시 • Oct 27Andes Technology Corporation has filed a Follow-on Equity Offering in the amount of TWD 118.35 million.Andes Technology Corporation has filed a Follow-on Equity Offering in the amount of TWD 118.35 million. Security Name: Shares Security Type: Common Stock Securities Offered: 450,000 Price\Range: TWD 263공시 • May 06Andes Technology Corporation has filed a Follow-on Equity Offering.Andes Technology Corporation has filed a Follow-on Equity Offering. Security Name: Common Shares Security Type: Common Stock Securities Offered: 1,000,000 Security Name: Common Shares Security Type: Common Stock Securities Offered: 4,000,000 Transaction Features: Rights Offering공시 • Apr 29Andes Technology Corporation to Report Q1, 2025 Results on May 05, 2025Andes Technology Corporation announced that they will report Q1, 2025 results at 9:00 AM, Taipei Standard Time on May 05, 2025공시 • Apr 24Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based PlatformAndes Technology in collaboration with Imagination Technologies announced the successful demonstration of Android 15 (Vanilla Ice Cream) running on a high-performance RISC-V-based hardware system. This achievement highlights the growing potential of RISC-V as a platform for rich operating systems and advanced graphical applications. The demonstration leverages Andes' Voyager Board, powered by its Qilai SoC, in combination with Imagination's GPU integrated within a graphics card. Together, the companies are showcasing a highly capable, fully operational Android system built on open hardware standards. The demonstration will be featured at the 2025 Andes RISC-V CON Silicon Valley, taking place on April 29th at the Doubletree by Hilton Hotel in San Jose. At the heart of the demonstration is a Voyager Development Board, built around Andes' 7nm Qilai RISC-V SoC. Key features include: Quad-core Andes AX45MP running at 2.2 GHz, powering the Android kernel. This processor is Andes' most widely licensed for rich OS environments, offering a strong balance of performance, power efficiency, and area optimization. NX27V Vector Processor at 1.5 GHz, featuring a 512-bit Vector Processing Unit (VPU) designed for parallel data processing -- ideal for machine learning, image processing, and signal processing workloads. Graphics performance is enables by the Imagination BXT-32-1024 GPU integrated into the graphics card, which delivers: 48 Gpixels/sec fill rate; 1.5 TFLOPS (FP32) of floating-point performance; Dual 4K display support at 60 fps; Full compatibility with modern graphics and compute APIs including OpenGL ES 3.2, Vulkan 1.3, and OpenCL 3.0. This powerful combination ensures a responsive and immersive Android experience on RISC-V hardware. This demonstration marks a significant milestone in the evolution of RISC-V and GPU integration. The powerful combination of Andes' RISC-V CPU cores and Imagination's cutting-edge GPU capabilities opens up new possibilities for embedded, AI and high-performance Android applications.공시 • Mar 07Andes Technology Corporation, Annual General Meeting, May 29, 2025Andes Technology Corporation, Annual General Meeting, May 29, 2025. Location: 4 floor no,1, kung yeh tung 2nd rd., hsinchu science park, hsinchu city Taiwan공시 • Feb 27Andes Technology Corporation to Report Q4, 2024 Results on Mar 06, 2025Andes Technology Corporation announced that they will report Q4, 2024 results on Mar 06, 2025공시 • Nov 01Andes Technology Corporation to Report Q3, 2024 Results on Nov 08, 2024Andes Technology Corporation announced that they will report Q3, 2024 results on Nov 08, 2024공시 • Oct 18Andes Announces the AndesCore AX66 supporting RVA23, Multi-cluster, Hypervisor and AndroidAndes Technology announced the AndesCore AX66 out-of-order superscalar multicore processor IP supporting the RVA23 profile. The AX66 is the 2nd member of the high-performance out-of-order AX60 series. Built on the success of the AX65 with the same 13-stage pipeline, 4-wide decode, and 8-wide out-of-order execution, the AX66 introduces many new features, including Vector and Vector Crypto support, Hypervisor and AIA, Multi-Cluster support with CHI, and RVA23 profile support. AX66's versatile capabilities on performance scalability, multimedia, security, and virtualization makes it an ideal main processor in high-performance Linux and Android applications such as edge/data center AI, infotainment, networking, and vision/camera applications. The AX66 boosts the SpecInt2006 performance over the 1st generation AX65 by more than 15%. Each core has 64KB private L1 instruction and data caches and up to 1MB private L2 cache, and each cluster contains up to 8 cores and a shared L3 cache up to 32MB. Besides the IO coherence interface already in the AX65, the AX66 adds a Coherence Hub Interface (CHI) for multi-cluster coherence. With the CHI interface support, the company can use much more AX66 CPUs to work together in the same cache-coherent domain. Together with the Hypervisor, AIA and optional IOMMU technologies, the AX66 can fully virtualize the entire multi-cluster CPU subsystem for resource sharing and security. Moreover, the AX66 supports the RISC-V standard external debug and instruction trace interfaces to facilitate fast system development, analysis and debugging. The AndesCore™? AX 66 is to be available for lead customers in Fourth Quarter 2024 through the early access program and for general customers in 2025.공시 • Jul 30Andes Technology Corporation to Report Q2, 2024 Results on Aug 06, 2024Andes Technology Corporation announced that they will report Q2, 2024 results on Aug 06, 2024공시 • May 26+ 1 more updateAndes Technology Corporation Announces Expiration of the Term of 3Rd Remuneration Committee MembersAndes Technology Corporation announced expiration of the term of 3rd Remuneration Committee members. Name of the previous position holder: Chien-Kuo Yang, Tien-Fu Chen and Jiun-Hao Lai. Resume of the previous position holder: Chien-Kuo Yang: Independent Director, Andes Technology Corp. Tien-Fu Chen: Independent Director, Andes Technology Corp. Jiun-Hao Lai: Independent Director, Andes Technology Corp. Name of the new position holder: To be appointed. Reason for the change: term expired.공시 • May 01Andes Technology Corporation to Report Q1, 2024 Results on May 07, 2024Andes Technology Corporation announced that they will report Q1, 2024 results on May 07, 2024공시 • Mar 07Andes Technology Corporation, Annual General Meeting, May 24, 2024Andes Technology Corporation, Annual General Meeting, May 24, 2024. Location: No.1, Gongye E. 2nd Rd., Hsinchu Science Park (4F, Meeting Room: Bach) Taiwan Agenda: To consider Report 2023 business report; to consider Audit Committee's review report; to consider Report on 2023 employees' profit sharing bonus and directors' compensation; to consider Report on the 2023 cash dividend distribution; to consider Amendment to the Company's" Sustainable Development Best Practice; to consider Adoption of the 2023 business report and financial statements; and to consider other matters.공시 • Jan 05Andes Technology Corporation Announces General Availability of the New RISC-V Out-Of-Order Superscalar Multicore Processor, the AndesCore™ AX65Andes Technology Corporation announced general availability of the high-performance AndesCore™ AX65 out-of-order superscalar multicore processor IP. The AX65 is the first of the high-performance out-of-order AX60 series. Equipped with 13-stage pipeline, 4-wide decode, 8-wide out-of-order execution, AX65 targets the Linux application processor sockets of computing, networking, and high-end controllers. It also received "Best IP/Processor of the Year" Award from EE Times Asia last December. Andes has been very successful on the embedded controllers and high-performance AI vector processors. As RISC-V ecosystem for Linux is getting matured, the demand for high-performance RISC-V processors for general-purpose applications rises. Andes takes this opportunity to introduce the AX65 to complete its comprehensive CPU lineup, spanning from low-power embedded solutions to high-end Out-of-Order processors. Customers who develop complex SOC can now use AX65 as the primary Linux application processor, the AX45MPV/NX27V for the vector/DSP processing and the N25/N225 processors as the resource and power manager. Leveraging the entire range of CPUs in the AndesCore™? families enables customers to streamline their development process, benefit from integrated support, and significantly reduce development cost. The AX65 operates at speeds exceeding 2.0GHz on a 12nm process, boasting a SpecInt2006 score of 8.25 per GHz -- outperforming the Cortex A75 with an efficient memory hierarchy. It also supports up to 8-core cache coherence with maximum 8MB shared cache. The AX65 is fully compliant with the RISC-V RVA22 profile, ensuring compatibility with operating systems and software within the RISC-V ecosystem. On the security side, AX65 supports Enhanced PMP (ePMP) for further securing memory accesses, and K (scalar cryptography) extension for accelerating AES and SHA crypto operations. For running Linux OS, the AX65 supports VIPT L1 instruction cache, SV48 virtual address space, and 2-level TLB with simultaneous hardware page walkers. It also incorporates branch prediction mechanism with TAGE-L algorithm, return address stack and 2-level branch target buffer. The AX65 can be used as an application processor in networking applications like Wi-Fi, 5Gnr, and O-RAN, as well as in edge computing and industrial PCs. Furthermore, it is well-suited for serving as the primary controller processor in embedded applications.공시 • Oct 18Andes Technology Unveils Andes D23 and N225 Cores Pioneering the Next Generation of Compact, Performant, and Secure RISC-V Processor TechnologyAndes Technology announced the release of its latest innovation - the AndesCore™? D23 and N225 RISC-V processors. Specifically designed to cater to the dynamic needs of the Internet of Things (IoT) and embedded systems, these cores epitomize Andes' unwavering commitment to delivering cutting-edge technology for the interconnected world. The D23 and N225 cores have been meticulously engineered with compactness, performance-efficiency, low-power consumption, flexibility, and security as top priorities. These cores empower IoT and embedded chip and device manufacturers to meet the burgeoning demands of a rapidly evolving market while minimizing power usage and ensuring robust security. Andes announced the popular N22, a 2-stage pipeline AndesCore implementing RV32I/EMAC ISA back in February 2019, targeting deeply embedded processing and having a performance of 3.95 Coremark/MHz and 1.8 DMIPS/MHz. The D23 and N 225 are revamped designs with a new microarchitecture and the latest RISC-V extensions to offer better performance, smaller code size, and more security support. They provide a good migration path for customers looking to upgrade their N22 designs or kick-off a new design. Common Key Features of AndesCore D23 and N225: Latest RISC-V Extensions Support: The N225 implements the RV32 IMACBZce non-privileged extensions as well as Machine/User modes and Enhanced Physical Memory Protection (ePMP). The D23 additionally supports the FDKP extensions (Single/Double-Precision Floating-Point, Scalar Crypto and Packed SIMD/DSP draft), and CMO (Cache Management Operations) extension. The D23 is also incorporated with Supervisor mode and its associated PMP (sPMP) for higher security. High Performance: Both cores achieve performance in their class, boasting outstanding benchmark scores such as 4.55 (D23) and 4.4 (N225) Coremark/MHz, and 2.08 (D23) and 1.92 (N225) DMIPS/MHz, respectively. They are capable of operating at high frequencies across various technology nodes such as near 800 MHz at 28nm, providing the necessary computing power for edge IoT devices with ever-increasing performance and feature demands. Power Management: Both cores support advanced power management technologies such as PowerBrake and Wait-For-Interrupt (WFI) and Wait-For-Event (WFE), ensuring prolonged battery life for many types of untethered IoT devices. Small Code Size: The N22 already offers code size with Andes CoDense™? technology. With the addition of the new RISC-V Zce code size reduction extension, the D23 and N225 further reduce 4.4% code size for the Embench-IoT benchmark, compared to the N22. This provides additional memory cost-saving for Andes customers. Flexibility: Both cores offer extensive configurability, including optimized multipliers for performance or area, optional static or dynamic branch prediction, various combinations of privilege modes, instruction and data. Local memories with sizes from 1 KB to 512 MB, and 2-wire or 4-wire JTAG debug interface. Designers can tailor these features to address their specific application requirements. In addition to the above-mentioned shared features and latest RISC-V extensions, the D23 core boasts additional capabilities, including built-in instruction and data cache, and ECC soft error protection for all cache and local memories. It can also seamlessly integrate with the powerful ACE™? (Andes Custom Extension) to support custom instructions for Domain-Specific Acceleration (DSA) and has a roadmap to include a functional safety derivative. These expanded capabilities open up opportunities for the D23 to serve a wider range of segments in automotive and industrial control applications.공시 • Sep 09Andes Technology Announces General Availability of the New Andescore Risc-V Multicore Vector Processor Ax45mpvAndes Technology announced general availability of the high-performance AndesCore™? AX45MPV multicore vector processor IP. The AX45MPV is the third generation of the award winning AndesCore™? vector processor series. Equipped with powerful RISC-V vector processing and parallel execution capability, it targets the applications with large volumes of data such as ADAS, AI inference and training, AR/VR, multimedia, robotics, and signal processing. Andes and Meta started collaboration on datacenter AI with RISC-V vector core from early 2019. Andes later unveiled the AndesCore™? NX27V, marking a significant milestone as the industry's first commercial RISC-V vector processor core with the capability of generating up to 4 512-bit vector (VLEN) results per cycle, at the end of 2019. It immediately attracted the attention of worldwide SoC design teams working on AI accelerators, and has landed over a dozen datacenter AI projects. Since then, the RISC-V vector processor cores have become the choice for ML and AI chip vendors. With the goal to further raise the compute density, the AX45MPV extends the capabilities of the dual-issue 8-stage pipeline, Linux support and multicore of the AX45MP with the powerful vector processing unit inherited and enhanced from its predecessor, the NX27V. While the AX45MPV is essentially a Linux application processor with datacenter grade AI capabilities, its support for Linux and multicore can be left out to form an efficient and powerful compute processor in processing elements (PEs) of a large compute array. The AX45MPV also supports the latest ACE (Andes Custom Extension™?), which facilitates customers to create their own RISC-V styled vector instructions. For example, ACE can be used to accelerate nonlinear math functions such as SoftMax on Transformer AI. Some customers from Asia and North America have already licensed the AX45MPV, and more are evaluating it. Their applications cover a wide range from the cloud to the edge. The AX45MPV standard product package, without Linux support, is available immediately. Its advanced product package will come with Linux support and will be available in Fourth Quarter 2023.이익 및 매출 성장 예측BDL:ANDA - 애널리스트 향후 추정치 및 과거 재무 데이터 (TWD Millions)날짜매출이익자유현금흐름영업현금흐름평균 애널리스트 수12/31/20272,525423413423112/31/20261,93022767568523/31/20261,533-467-1,083180N/A12/31/20251,478-415-948310N/A9/30/20251,479-257-1,098140N/A6/30/20251,441-267-991178N/A3/31/20251,440-62-806325N/A12/31/20241,3822-785372N/A9/30/20241,326-240-1,101-29N/A6/30/20241,145-134-834180N/A3/31/20241,046-98-85892N/A12/31/20231,058-102-863-69N/A9/30/2023961-125-61788N/A6/30/202398563-408190N/A3/31/2023946177-77438N/A12/31/2022932356261718N/A9/30/2022891519409783N/A6/30/2022812270213531N/A3/31/2022880258177436N/A12/31/202182016290311N/A9/30/2021819252131328N/A6/30/202173217891269N/A3/31/2021626101-9164N/A12/31/202058135-56110N/A9/30/2020446-75-11942N/A6/30/2020469-41-11242N/A3/31/20205222-8662N/A12/31/201949516N/A31N/A9/30/201948746N/A41N/A6/30/201941635N/A53N/A3/31/201934839N/A43N/A12/31/201830542N/A-8N/A9/30/20182362N/A33N/A6/30/201824726N/A-13N/A3/31/20182420N/A34N/A12/31/201728922N/A42N/A9/30/201731740N/A15N/A6/30/201730816N/A2N/A3/31/2017257-9N/A-44N/A12/31/2016209-32N/A-45N/A9/30/2016182-49N/A-84N/A6/30/2016170-49N/A-46N/A3/31/2016193-25N/A-38N/A12/31/20152194N/A1N/A9/30/2015207-1N/A8N/A6/30/20152082N/A-11N/A더 보기애널리스트 향후 성장 전망수입 대 저축률: ANDA 은 향후 3년 동안 수익을 낼 것으로 예상되며, 이는 절약률(3.5%)보다 빠른 성장으로 간주됩니다.수익 vs 시장: ANDA (는) 향후 3년 동안 평균 시장 성장보다 높은 수익을 올릴 것으로 예상됩니다.고성장 수익: ANDA 향후 3년 내에 수익을 낼 것으로 예상됩니다.수익 대 시장: ANDA 의 수익(연간 28.2%)이 Luxembourg 시장(연간 5.3%)보다 빠르게 성장할 것으로 예상됩니다.고성장 매출: ANDA 의 수익(연간 28.2%)은 연간 20%보다 빠르게 증가할 것으로 예상됩니다.주당순이익 성장 예측향후 자기자본이익률미래 ROE: ANDA의 자본 수익률이 3년 후 높을 것으로 예상되는지 판단하기에 데이터가 부족합니다.성장 기업 찾아보기7D1Y7D1Y7D1YSemiconductors 산업의 고성장 기업.View Past Performance기업 분석 및 재무 데이터 상태데이터최종 업데이트 (UTC 시간)기업 분석2026/05/22 19:01종가2026/05/22 00:00수익2026/03/31연간 수익2025/12/31데이터 소스당사의 기업 분석에 사용되는 데이터는 S&P Global Market Intelligence LLC에서 제공됩니다. 아래 데이터는 이 보고서를 생성하기 위해 분석 모델에서 사용됩니다. 데이터는 정규화되므로 소스가 제공된 후 지연이 발생할 수 있습니다.패키지데이터기간미국 소스 예시 *기업 재무제표10년손익계산서현금흐름표대차대조표SEC 양식 10-KSEC 양식 10-Q분석가 컨센서스 추정치+3년재무 예측분석가 목표주가분석가 리서치 보고서Blue Matrix시장 가격30년주가배당, 분할 및 기타 조치ICE 시장 데이터SEC 양식 S-1지분 구조10년주요 주주내부자 거래SEC 양식 4SEC 양식 13D경영진10년리더십 팀이사회SEC 양식 10-KSEC 양식 DEF 14A주요 개발10년회사 공시SEC 양식 8-K* 미국 증권에 대한 예시이며, 비(非)미국 증권에는 해당 국가의 규제 서식 및 자료원을 사용합니다.별도로 명시되지 않는 한 모든 재무 데이터는 연간 기간을 기준으로 하지만 분기별로 업데이트됩니다. 이를 TTM(최근 12개월) 또는 LTM(지난 12개월) 데이터라고 합니다. 자세히 알아보기.분석 모델 및 스노우플레이크이 보고서를 생성하는 데 사용된 분석 모델에 대한 자세한 내용은 당사의 Github 페이지에서 확인하실 수 있습니다. 또한 보고서 활용 방법에 대한 가이드와 YouTube 튜토리얼도 제공합니다.Simply Wall St 분석 모델을 설계하고 구축한 세계적 수준의 팀에 대해 알아보세요.산업 및 섹터 지표산업 및 섹터 지표는 Simply Wall St가 6시간마다 계산하며, 프로세스에 대한 자세한 내용은 Github에서 확인할 수 있습니다.분석가 소스Andes Technology Corporation는 9명의 분석가가 다루고 있습니다. 이 중 2명의 분석가가 우리 보고서에 입력 데이터로 사용되는 매출 또는 수익 추정치를 제출했습니다. 분석가의 제출 자료는 하루 종일 업데이트됩니다.분석가기관Rick HsuDaiwa Securities Co. Ltd.Yi-Chun LinDaiwa Securities Co. Ltd.Wei Lun YangJ.P. Morgan6명의 분석가 더 보기
공시 • Mar 10Andes Technology Corporation, Annual General Meeting, May 28, 2026Andes Technology Corporation, Annual General Meeting, May 28, 2026, at 10:00 Taipei Standard Time. Location: 4 floor no,1, kung yeh tung 2nd rd., hsinchu science park, hsinchu city Taiwan
공시 • Oct 27Andes Technology Corporation has filed a Follow-on Equity Offering in the amount of TWD 118.35 million.Andes Technology Corporation has filed a Follow-on Equity Offering in the amount of TWD 118.35 million. Security Name: Shares Security Type: Common Stock Securities Offered: 450,000 Price\Range: TWD 263
공시 • May 06Andes Technology Corporation has filed a Follow-on Equity Offering.Andes Technology Corporation has filed a Follow-on Equity Offering. Security Name: Common Shares Security Type: Common Stock Securities Offered: 1,000,000 Security Name: Common Shares Security Type: Common Stock Securities Offered: 4,000,000 Transaction Features: Rights Offering
공시 • Apr 29Andes Technology Corporation to Report Q1, 2025 Results on May 05, 2025Andes Technology Corporation announced that they will report Q1, 2025 results at 9:00 AM, Taipei Standard Time on May 05, 2025
공시 • Apr 24Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based PlatformAndes Technology in collaboration with Imagination Technologies announced the successful demonstration of Android 15 (Vanilla Ice Cream) running on a high-performance RISC-V-based hardware system. This achievement highlights the growing potential of RISC-V as a platform for rich operating systems and advanced graphical applications. The demonstration leverages Andes' Voyager Board, powered by its Qilai SoC, in combination with Imagination's GPU integrated within a graphics card. Together, the companies are showcasing a highly capable, fully operational Android system built on open hardware standards. The demonstration will be featured at the 2025 Andes RISC-V CON Silicon Valley, taking place on April 29th at the Doubletree by Hilton Hotel in San Jose. At the heart of the demonstration is a Voyager Development Board, built around Andes' 7nm Qilai RISC-V SoC. Key features include: Quad-core Andes AX45MP running at 2.2 GHz, powering the Android kernel. This processor is Andes' most widely licensed for rich OS environments, offering a strong balance of performance, power efficiency, and area optimization. NX27V Vector Processor at 1.5 GHz, featuring a 512-bit Vector Processing Unit (VPU) designed for parallel data processing -- ideal for machine learning, image processing, and signal processing workloads. Graphics performance is enables by the Imagination BXT-32-1024 GPU integrated into the graphics card, which delivers: 48 Gpixels/sec fill rate; 1.5 TFLOPS (FP32) of floating-point performance; Dual 4K display support at 60 fps; Full compatibility with modern graphics and compute APIs including OpenGL ES 3.2, Vulkan 1.3, and OpenCL 3.0. This powerful combination ensures a responsive and immersive Android experience on RISC-V hardware. This demonstration marks a significant milestone in the evolution of RISC-V and GPU integration. The powerful combination of Andes' RISC-V CPU cores and Imagination's cutting-edge GPU capabilities opens up new possibilities for embedded, AI and high-performance Android applications.
공시 • Mar 07Andes Technology Corporation, Annual General Meeting, May 29, 2025Andes Technology Corporation, Annual General Meeting, May 29, 2025. Location: 4 floor no,1, kung yeh tung 2nd rd., hsinchu science park, hsinchu city Taiwan
공시 • Feb 27Andes Technology Corporation to Report Q4, 2024 Results on Mar 06, 2025Andes Technology Corporation announced that they will report Q4, 2024 results on Mar 06, 2025
공시 • Nov 01Andes Technology Corporation to Report Q3, 2024 Results on Nov 08, 2024Andes Technology Corporation announced that they will report Q3, 2024 results on Nov 08, 2024
공시 • Oct 18Andes Announces the AndesCore AX66 supporting RVA23, Multi-cluster, Hypervisor and AndroidAndes Technology announced the AndesCore AX66 out-of-order superscalar multicore processor IP supporting the RVA23 profile. The AX66 is the 2nd member of the high-performance out-of-order AX60 series. Built on the success of the AX65 with the same 13-stage pipeline, 4-wide decode, and 8-wide out-of-order execution, the AX66 introduces many new features, including Vector and Vector Crypto support, Hypervisor and AIA, Multi-Cluster support with CHI, and RVA23 profile support. AX66's versatile capabilities on performance scalability, multimedia, security, and virtualization makes it an ideal main processor in high-performance Linux and Android applications such as edge/data center AI, infotainment, networking, and vision/camera applications. The AX66 boosts the SpecInt2006 performance over the 1st generation AX65 by more than 15%. Each core has 64KB private L1 instruction and data caches and up to 1MB private L2 cache, and each cluster contains up to 8 cores and a shared L3 cache up to 32MB. Besides the IO coherence interface already in the AX65, the AX66 adds a Coherence Hub Interface (CHI) for multi-cluster coherence. With the CHI interface support, the company can use much more AX66 CPUs to work together in the same cache-coherent domain. Together with the Hypervisor, AIA and optional IOMMU technologies, the AX66 can fully virtualize the entire multi-cluster CPU subsystem for resource sharing and security. Moreover, the AX66 supports the RISC-V standard external debug and instruction trace interfaces to facilitate fast system development, analysis and debugging. The AndesCore™? AX 66 is to be available for lead customers in Fourth Quarter 2024 through the early access program and for general customers in 2025.
공시 • Jul 30Andes Technology Corporation to Report Q2, 2024 Results on Aug 06, 2024Andes Technology Corporation announced that they will report Q2, 2024 results on Aug 06, 2024
공시 • May 26+ 1 more updateAndes Technology Corporation Announces Expiration of the Term of 3Rd Remuneration Committee MembersAndes Technology Corporation announced expiration of the term of 3rd Remuneration Committee members. Name of the previous position holder: Chien-Kuo Yang, Tien-Fu Chen and Jiun-Hao Lai. Resume of the previous position holder: Chien-Kuo Yang: Independent Director, Andes Technology Corp. Tien-Fu Chen: Independent Director, Andes Technology Corp. Jiun-Hao Lai: Independent Director, Andes Technology Corp. Name of the new position holder: To be appointed. Reason for the change: term expired.
공시 • May 01Andes Technology Corporation to Report Q1, 2024 Results on May 07, 2024Andes Technology Corporation announced that they will report Q1, 2024 results on May 07, 2024
공시 • Mar 07Andes Technology Corporation, Annual General Meeting, May 24, 2024Andes Technology Corporation, Annual General Meeting, May 24, 2024. Location: No.1, Gongye E. 2nd Rd., Hsinchu Science Park (4F, Meeting Room: Bach) Taiwan Agenda: To consider Report 2023 business report; to consider Audit Committee's review report; to consider Report on 2023 employees' profit sharing bonus and directors' compensation; to consider Report on the 2023 cash dividend distribution; to consider Amendment to the Company's" Sustainable Development Best Practice; to consider Adoption of the 2023 business report and financial statements; and to consider other matters.
공시 • Jan 05Andes Technology Corporation Announces General Availability of the New RISC-V Out-Of-Order Superscalar Multicore Processor, the AndesCore™ AX65Andes Technology Corporation announced general availability of the high-performance AndesCore™ AX65 out-of-order superscalar multicore processor IP. The AX65 is the first of the high-performance out-of-order AX60 series. Equipped with 13-stage pipeline, 4-wide decode, 8-wide out-of-order execution, AX65 targets the Linux application processor sockets of computing, networking, and high-end controllers. It also received "Best IP/Processor of the Year" Award from EE Times Asia last December. Andes has been very successful on the embedded controllers and high-performance AI vector processors. As RISC-V ecosystem for Linux is getting matured, the demand for high-performance RISC-V processors for general-purpose applications rises. Andes takes this opportunity to introduce the AX65 to complete its comprehensive CPU lineup, spanning from low-power embedded solutions to high-end Out-of-Order processors. Customers who develop complex SOC can now use AX65 as the primary Linux application processor, the AX45MPV/NX27V for the vector/DSP processing and the N25/N225 processors as the resource and power manager. Leveraging the entire range of CPUs in the AndesCore™? families enables customers to streamline their development process, benefit from integrated support, and significantly reduce development cost. The AX65 operates at speeds exceeding 2.0GHz on a 12nm process, boasting a SpecInt2006 score of 8.25 per GHz -- outperforming the Cortex A75 with an efficient memory hierarchy. It also supports up to 8-core cache coherence with maximum 8MB shared cache. The AX65 is fully compliant with the RISC-V RVA22 profile, ensuring compatibility with operating systems and software within the RISC-V ecosystem. On the security side, AX65 supports Enhanced PMP (ePMP) for further securing memory accesses, and K (scalar cryptography) extension for accelerating AES and SHA crypto operations. For running Linux OS, the AX65 supports VIPT L1 instruction cache, SV48 virtual address space, and 2-level TLB with simultaneous hardware page walkers. It also incorporates branch prediction mechanism with TAGE-L algorithm, return address stack and 2-level branch target buffer. The AX65 can be used as an application processor in networking applications like Wi-Fi, 5Gnr, and O-RAN, as well as in edge computing and industrial PCs. Furthermore, it is well-suited for serving as the primary controller processor in embedded applications.
공시 • Oct 18Andes Technology Unveils Andes D23 and N225 Cores Pioneering the Next Generation of Compact, Performant, and Secure RISC-V Processor TechnologyAndes Technology announced the release of its latest innovation - the AndesCore™? D23 and N225 RISC-V processors. Specifically designed to cater to the dynamic needs of the Internet of Things (IoT) and embedded systems, these cores epitomize Andes' unwavering commitment to delivering cutting-edge technology for the interconnected world. The D23 and N225 cores have been meticulously engineered with compactness, performance-efficiency, low-power consumption, flexibility, and security as top priorities. These cores empower IoT and embedded chip and device manufacturers to meet the burgeoning demands of a rapidly evolving market while minimizing power usage and ensuring robust security. Andes announced the popular N22, a 2-stage pipeline AndesCore implementing RV32I/EMAC ISA back in February 2019, targeting deeply embedded processing and having a performance of 3.95 Coremark/MHz and 1.8 DMIPS/MHz. The D23 and N 225 are revamped designs with a new microarchitecture and the latest RISC-V extensions to offer better performance, smaller code size, and more security support. They provide a good migration path for customers looking to upgrade their N22 designs or kick-off a new design. Common Key Features of AndesCore D23 and N225: Latest RISC-V Extensions Support: The N225 implements the RV32 IMACBZce non-privileged extensions as well as Machine/User modes and Enhanced Physical Memory Protection (ePMP). The D23 additionally supports the FDKP extensions (Single/Double-Precision Floating-Point, Scalar Crypto and Packed SIMD/DSP draft), and CMO (Cache Management Operations) extension. The D23 is also incorporated with Supervisor mode and its associated PMP (sPMP) for higher security. High Performance: Both cores achieve performance in their class, boasting outstanding benchmark scores such as 4.55 (D23) and 4.4 (N225) Coremark/MHz, and 2.08 (D23) and 1.92 (N225) DMIPS/MHz, respectively. They are capable of operating at high frequencies across various technology nodes such as near 800 MHz at 28nm, providing the necessary computing power for edge IoT devices with ever-increasing performance and feature demands. Power Management: Both cores support advanced power management technologies such as PowerBrake and Wait-For-Interrupt (WFI) and Wait-For-Event (WFE), ensuring prolonged battery life for many types of untethered IoT devices. Small Code Size: The N22 already offers code size with Andes CoDense™? technology. With the addition of the new RISC-V Zce code size reduction extension, the D23 and N225 further reduce 4.4% code size for the Embench-IoT benchmark, compared to the N22. This provides additional memory cost-saving for Andes customers. Flexibility: Both cores offer extensive configurability, including optimized multipliers for performance or area, optional static or dynamic branch prediction, various combinations of privilege modes, instruction and data. Local memories with sizes from 1 KB to 512 MB, and 2-wire or 4-wire JTAG debug interface. Designers can tailor these features to address their specific application requirements. In addition to the above-mentioned shared features and latest RISC-V extensions, the D23 core boasts additional capabilities, including built-in instruction and data cache, and ECC soft error protection for all cache and local memories. It can also seamlessly integrate with the powerful ACE™? (Andes Custom Extension) to support custom instructions for Domain-Specific Acceleration (DSA) and has a roadmap to include a functional safety derivative. These expanded capabilities open up opportunities for the D23 to serve a wider range of segments in automotive and industrial control applications.
공시 • Sep 09Andes Technology Announces General Availability of the New Andescore Risc-V Multicore Vector Processor Ax45mpvAndes Technology announced general availability of the high-performance AndesCore™? AX45MPV multicore vector processor IP. The AX45MPV is the third generation of the award winning AndesCore™? vector processor series. Equipped with powerful RISC-V vector processing and parallel execution capability, it targets the applications with large volumes of data such as ADAS, AI inference and training, AR/VR, multimedia, robotics, and signal processing. Andes and Meta started collaboration on datacenter AI with RISC-V vector core from early 2019. Andes later unveiled the AndesCore™? NX27V, marking a significant milestone as the industry's first commercial RISC-V vector processor core with the capability of generating up to 4 512-bit vector (VLEN) results per cycle, at the end of 2019. It immediately attracted the attention of worldwide SoC design teams working on AI accelerators, and has landed over a dozen datacenter AI projects. Since then, the RISC-V vector processor cores have become the choice for ML and AI chip vendors. With the goal to further raise the compute density, the AX45MPV extends the capabilities of the dual-issue 8-stage pipeline, Linux support and multicore of the AX45MP with the powerful vector processing unit inherited and enhanced from its predecessor, the NX27V. While the AX45MPV is essentially a Linux application processor with datacenter grade AI capabilities, its support for Linux and multicore can be left out to form an efficient and powerful compute processor in processing elements (PEs) of a large compute array. The AX45MPV also supports the latest ACE (Andes Custom Extension™?), which facilitates customers to create their own RISC-V styled vector instructions. For example, ACE can be used to accelerate nonlinear math functions such as SoftMax on Transformer AI. Some customers from Asia and North America have already licensed the AX45MPV, and more are evaluating it. Their applications cover a wide range from the cloud to the edge. The AX45MPV standard product package, without Linux support, is available immediately. Its advanced product package will come with Linux support and will be available in Fourth Quarter 2023.