공시 • Apr 21
Alchip Technologies Announces Appointment of Freddy Engineer as Chief Business Officer of Alchip North America Alchip Technologies announced the appointment of Mr. Freddy Engineer as Chief Business Officer (CBO) and General Manager of Alchip North America. In this role, Mr. Engineer will lead the company’s global business growth strategy while accelerating expansion of the U.S. market. Mr. Engineer will oversee worldwide sales and lead the North America Business Unit. His mandate includes expanding customer relationships, strengthening go-to-market execution, and aligning global teams to support the growing demand for the company’s high-performance custom ASIC solutions. Mr. Engineer brings more than two decades of leadership experience across the data center, communications, and cloud infrastructure markets. Most recently, he served as GM of the Semi-Custom Silicon Business at NVIDIA, where he led global business development initiatives for cloud service providers, hyperscalers, and communications customers. Prior to NVIDIA, he spent approximately 25 years at Xilinx Inc. holding several senior leadership positions, including Corporate Vice President and General Manager of the Data Center Business. During his tenure, Mr. Engineer built and scaled Xilinx’s data center organization, strengthening strategic partnerships with Tier-1 hyperscalers and other key customers. Mr. Engineer’s background in global sales, strategic accounts, and field applications engineering positions him to bridge technology strategy with customer needs as demand for Alchip’s ASIC from AI and data center enterprises continues to scale. 공시 • Apr 17
Alchip Technologies Announces 3Dic Platform for Next-Generation Ai Processors Alchip Technologies said its 3DIC platform is driving more efficient development of next-generation AI and high-performance computing devices through flexible chiplet architectures and advanced packaging integration. AI infrastructure is in a new phase of system-level complexity. Scaling performance depends on more than transistor density. It comes down to how efficiently multiple compute dies, memory stacks, and interconnect fabrics operate as a single system. Designers are balancing performance, bandwidth, power, thermals, and manufacturability—simultaneously. Next-generation AI accelerators demand multi-terabyte-per-second memory bandwidth. Data movement consumes a growing share of total system power. Large monolithic dies face reticle limits, lower yields, and rising mask costs. Even traditional 2.5D approaches introduce interposer complexity, package size constraints, and limited flexibility for vertical integration. Alchip’s 3.5D ASIC platform addresses these challenges with a system-level approach to heterogeneous integration. It partitions large SoCs into optimized chiplets across multiple process nodes. Compute dies scale on leading-edge technologies, while I/O and memory functions remain on cost-efficient nodes to improve yield, reduces cost, and accelerates deployment. The platform combines horizontal chiplet scaling with selective vertical die stacking. This hybrid 3.5D architecture delivers higher interconnect density and significantly greater design flexibility than conventional approaches. Alchip integrates this architecture with advanced packaging technologies including CoWoS-S, CoWoS-R, CoWoS-L, and TSMC-SoIC-X. The result is high-bandwidth, low-latency die-to-die connectivity that supports multi-terabyte-per-second aggregate throughput. The platform is currently delivering up to 3–5x higher interconnect density using 30-40% less energy per bit at a lower latency of up to 35%. The platform co-designs die placement, heat dissipation, and power delivery to improve efficiency. Shorter vertical power paths and optimized power delivery networks enhance performance. Integrated thermal strategies support advanced data center cooling approaches. The 3DIC platform also provides a unified design and integration flow across silicon, packaging, and system layers. This reduces development friction and allows designers to focus on workload optimization rather than infrastructure integration. Alchip’s 3DIC platform is ideal for hyperscale cloud providers, AI accelerator startups, and HPC system companies developing custom silicon. A typical configuration may include multiple compute chiplets on advanced nodes, I/O dies on mature nodes, and HBM stacks within a single package. Systems are now reaching multi-kilowatts powers levels. The ASIC platform extends the company’s long-standing leadership in advanced-node ASIC design and 2.5D/3DIC integration. 공시 • Mar 09
Alchip Technologies, Limited, Annual General Meeting, May 26, 2026 Alchip Technologies, Limited, Annual General Meeting, May 26, 2026. Location: 3 floor no,168, ching yeh 4th rd., jhongshan district, taipei city Taiwan 공시 • Sep 04
Alchip 3DIC Test Chip Tape Out Validates Ecosystem Readiness Alchip Technologies validated its 3DIC ecosystem readiness with results from its 3DIC test chip tape out. The results vaulted Alchip into a clear 3DIC technology leadership because it validated an entire, integrated 3DIC solution, as well as its various elements. The test chip provided CPU/NPU core demonstration, UCIe and PCIe PHY preparation, Lite-IO infrastructure, and third-party IP. The latter is particularly important because any 3DIC proven IP is hard to find. Alchip's 3DIC test chip success holds greater than normal implications because it provided technical validation of the company's 3DIC ecosystem. Alchip's growing ASIC ecosystem assures AI and HPC developers of a fast time-to-design, accurate pathway for highly complex ASIC devices. Alchip's ecosystem encompasses a technology-specific design flow, package design flow, die-to-die IP, and interconnect. Tape out validation is a critical step because 3DIC elements differ significantly from their 2D counterparts. Alchip's device integrates a 3nm top die and a 5nm base die, assembled using TSMC's SoIC®?-X packaging technology. It is designed to stress test power density and thermal dissipation challenges inherent in 3D integration. The results also inform future 3DIC designs incorporating 2nm and 3nm stacked chiplets. The chip includes a CPU, NPU core and high-power logic on the top die. The base die integrates a network-on-chip, L3 cache, and interface IP. The two dies are connected using APLink-3D Lite IO. The tape out validated several critical 3DIC capabilities, including: Cross-die synchronous die-to-die IP. Design-for-test strategies with redundancy, repair, and process monitoring. Signal and power integrity analysis for 3D stacking. Thermal and mechanical simulations for vertical integration. 3D physical design implementation and verification. The dual-die design required a new approach to physical and logical integration. The EDA tools and design methods were updated to support co-design across both dies. Sign-off included electrical, timing, and mechanical integrity across the full 3D assembly. The company tested Interface IP, architected specifically for 3DIC. Interoperability and full functionality requested new IP. Each die, especially the bottom die, requires custom PHY implementations for protocols such as UCIe, and PCIe. 3DI/O timing represents another major advancement. Alchip has limited die-to-die latency to 40 picoseconds, enabling timing paths that span dies without degrading performance. A fully integrated 3D clocking structure ensure coherent operation across both layers with minimal timing skew. Four IP vendors participated in the test chip program. Two contributed proven hard macros. Two others evaluated new IP on the test platform. An EDA flow vendor collaborated to ensure tool and methodology readiness. 공시 • Jul 22
Alchip Technologies, Limited Introduces 2nm Design Platform Alchip Technologies, Limited has received the first wafers from its 2nm Design Platform and is actively engaged with customers on high performance 2nm ASIC development. The new 2nm Design Platform facilitates the physical design of a 2nm chip using multiple types of 2.5D/3D technologies. It supports the development of 5nm or 3nm IO chiplets that work in conjunction with 2nm compute dies. The complete physical design methodology supports technology up to 2nm, and advanced packaging including CoWoS®?-S/R/L 2.5D/3D/3D package, System on Integrated Chips (TSMC-SoIC®?-X), die-to-die IP, and IO chiplet design. System on Wafer (TSMC-SoW™?) 3DIC solutions are on track to be supported as well. The 2nm process node introduces a complex layout structure, with a significantly greater variety of standard cells that make placement and signal/power routing more challenging. Alchip's design methodology reduces turnaround time in both design implementation and verification by proactively addressing all side effects before floor planning and clock/power planning stages. From a packaging standpoint, power density and thermal dissipation per mm2 at the 2nm node are higher because of a larger gate count and faster operating speed. While 2nm IO chiplets are not yet available, Alchip's 2nm Design Platform provides the more practical approach, enabling 2nm compute dies to work seamlessly with 3nm or 5nm IO chiplets. Alchip's 2nm test chip achieved first-pass silicon success, reinforcing the company's high-performance ASIC leadership. The chip successfully integrated Alchip's AP-Link-3D I/O IP, demonstrating its readiness for 3D SoIC-X chiplet applications. The results also lay a foundation for the company's migration to TSMC's A16™? process node. 공시 • May 30
Alchip Technologies, Limited Approves the Election of Directors Alchip Technologies, Limited at its AGM held on May 29, 2025, approved the election of Directors: Herbert Chang and Independent Directors: Andrew Kuo, Jerry Tzou, Derek C.Y. Tien and Saria Tseng. 
