공지 • May 08
Rambus Inc Introduces PCIe 7.0 Switch Ip With Time Division Multiplexing Rambus Inc. announced the Rambus PCIe 7.0 Switch IP with Time Division Multiplexing, a new addition to its advanced interconnect IP portfolio designed to address the rapidly escalating bandwidth, latency, and scalability requirements of AI, cloud, and high-performance computing (HPC) systems. Rambus PCIe 7.0 Switch IP with Time Division Multiplexing enables efficient, scalable PCIe fabrics that optimize link utilization and reduce system complexity for scale up and scale out of distributed AI clusters and high-performance computing networks. Supports bandwidth scaling, low latency, and efficient data movement for AI, cloud, and HPC systems. Increases link utilization through intelligent traffic multiplexing, enabling simpler architectures and scalable disaggregated and pooled compute designs. Extends the Rambus PCIe IP portfolio which spans switches, controllers, retimers, and debug solutions to support next-generation AI infrastructure. As AI infrastructure grows in scale and architectural complexity, system designers are increasingly challenged to move massive volumes of data efficiently across CPUs, GPUs, accelerators, and NVMe storage. The Rambus PCIe 7.0 Switch IP with Time Division Multiplexing is architected to help meet these demands by enabling more flexible and efficient utilization of PCIe links, supporting emerging disaggregated and pooled compute architectures while maintaining low latency and deterministic performance. Built on the PCIe 7.0 specification, the Rambus newest switch IP is optimized for next-generation AI and data center SoCs that require extreme bandwidth density, advanced traffic management, and seamless scalability. By incorporating Time Division Multiplexing capabilities, the switch enables designers to intelligently schedule and multiplex traffic across shared links, helping maximize fabric utilization while supporting diverse workload profiles, from large-scale AI training to latency-sensitive inference and data movement. The Rambus PCIe 7.0 Switch IP with Time Division Multiplexing is designed to integrate seamlessly into ASIC platforms and complements Rambus’ PCIe 7.0 IP portfolio, which includes controllers, retimers, and debug solutions. These IP offerings help customers accelerate time-to-market while addressing the demanding performance, power, and reliability requirements of modern AI infrastructure. The Rambus PCIe 7.0 Switch IP with Time Division Multiplexing reinforces the company’s leadership in high-speed interface IP and its commitment to delivering differentiated interconnect technologies that help customers solve the most challenging problems in AI, cloud, and HPC Infrastructure. 공지 • Apr 29
Rambus Inc. Provides Earnings Guidance for the Second Quarter Ending June 30, 2026 Rambus Inc. provided earnings guidance for the second quarter ending June 30, 2026. For the quarter, the company expected royalty revenue to be between $72 million and $78 million, product revenue to be between $95 million and $101 million, and contract and other revenue to be between $19 million and $25 million. Reported Earnings • Apr 28
First quarter 2026 earnings released: EPS: US$0.55 (vs US$0.56 in 1Q 2025) First quarter 2026 results: EPS: US$0.55 (down from US$0.56 in 1Q 2025). Revenue: US$180.2m (up 8.1% from 1Q 2025). Net income: US$59.9m (flat on 1Q 2025). Profit margin: 33% (down from 36% in 1Q 2025). The decrease in margin was driven by higher expenses. Revenue is forecast to grow 14% p.a. on average during the next 3 years, compared to a 13% growth forecast for the Semiconductor industry in Europe. Valuation Update With 7 Day Price Move • Apr 25
Investor sentiment improves as stock rises 20% After last week's 20% share price gain to €130, the stock trades at a forward P/E ratio of 64x. Average forward P/E is 35x in the Semiconductor industry in Europe. Simply Wall St's valuation model estimates the intrinsic value at €56.06 per share. 공지 • Apr 23
Rambus Inc. Enables Power-Efficient AI Platforms with SOCAMM2 Server Module Chipset Rambus Inc. announced a SOCAMM2 (Small Outline Compression Attached Memory Module) chipset designed to enable low-power, high-performance LPDDR5X-based memory modules for AI server platforms. The SOCAMM2 chipset represents the first step in a broader Rambus roadmap of LPDDR-based server module solutions, reflecting the company’s ongoing collaboration with industry partners to support new memory architectures optimized for evolving workloads in AI data center infrastructure. This new product family extends the comprehensive Rambus offering of complete memory interface chipsets for all JEDEC-standard DDR5 and LPDDR5 memory modules. SOCAMM2 memory modules, based on LPDDR technology, are emerging as an innovative architectural approach to address these challenges by delivering high performance with lower power consumption in a modular, serviceable, board area efficient form factor. The Rambus SOCAMM2 chipset is designed to support this transition by providing the critical control, telemetry, and power delivery functions required by JEDEC-standard SOCAMM2 memory modules in demanding AI server environments. SOCAMM2 replaces soldered LPDDR memory with detachable, upgradable modules that combine LPDDR efficiency with server-class serviceability in the data center. The Rambus LPDDR5X SOCAMM2 chipset supports reliable, power-efficient operation of LPDDR-based server memory modules at up to 9.6 Gb/s and includes: SPD Hub for module identification, configuration, and telemetry; 12-amp (A) and 3A voltage regulators for localized, efficient power conversion. 
