Alchip Technologies（ALCHA）株式概要アルチップ・テクノロジーズ社（Alchip Technologies, Limited）は、その子会社とともに、日本、台湾、中国において、ファブレス特定用途向け集積回路（ASIC）およびシステムオンチップ（SOC）の研究開発、設計、製造を行っています。 詳細ALCHA ファンダメンタル分析スノーフレーク・スコア評価1/6将来の成長6/6過去の実績3/6財務の健全性6/6配当金0/6報酬収益は年間39.77%増加すると予測されています リスク分析Luxembourg市場と比較して、過去 3 か月間の株価の変動が非常に大きいすべてのリスクチェックを見るALCHA Community Fair Values Create NarrativeSee what others think this stock is worth. Follow their fair value or set your own to get alerts.Your Fair ValueUS$Current PriceUS$156.0077.5% 割安 内在価値ディスカウントGrowth estimate overAnnual revenue growth rate5 Yearstime period%/yrDecreaseIncreasePastFuture-183m199b2016201920222025202620282031Revenue NT$199.1bEarnings NT$45.0bAdvancedSet Fair ValueView all narrativesAlchip Technologies, Limited 競合他社Nexchip SemiconductorSymbol: SHSE:688249Market cap: CN¥75.9bTongfu MicroelectronicsLtdSymbol: SZSE:002156Market cap: CN¥96.3bKing Yuan ElectronicsSymbol: TWSE:2449Market cap: NT$361.9bSG MicroSymbol: SZSE:300661Market cap: CN¥68.9b価格と性能株価の高値、安値、推移の概要Alchip Technologies過去の株価現在の株価NT$156.0052週高値NT$052週安値NT$0ベータ1.171ヶ月の変化20.93%3ヶ月変化n/a1年変化57.58%3年間の変化217.07%5年間の変化716.75%IPOからの変化506.30%最新ニュースお知らせ • Apr 21Alchip Technologies Announces Appointment of Freddy Engineer as Chief Business Officer of Alchip North AmericaAlchip Technologies announced the appointment of Mr. Freddy Engineer as Chief Business Officer (CBO) and General Manager of Alchip North America. In this role, Mr. Engineer will lead the company’s global business growth strategy while accelerating expansion of the U.S. market. Mr. Engineer will oversee worldwide sales and lead the North America Business Unit. His mandate includes expanding customer relationships, strengthening go-to-market execution, and aligning global teams to support the growing demand for the company’s high-performance custom ASIC solutions. Mr. Engineer brings more than two decades of leadership experience across the data center, communications, and cloud infrastructure markets. Most recently, he served as GM of the Semi-Custom Silicon Business at NVIDIA, where he led global business development initiatives for cloud service providers, hyperscalers, and communications customers. Prior to NVIDIA, he spent approximately 25 years at Xilinx Inc. holding several senior leadership positions, including Corporate Vice President and General Manager of the Data Center Business. During his tenure, Mr. Engineer built and scaled Xilinx’s data center organization, strengthening strategic partnerships with Tier-1 hyperscalers and other key customers. Mr. Engineer’s background in global sales, strategic accounts, and field applications engineering positions him to bridge technology strategy with customer needs as demand for Alchip’s ASIC from AI and data center enterprises continues to scale.お知らせ • Apr 17Alchip Technologies Announces 3Dic Platform for Next-Generation Ai ProcessorsAlchip Technologies said its 3DIC platform is driving more efficient development of next-generation AI and high-performance computing devices through flexible chiplet architectures and advanced packaging integration. AI infrastructure is in a new phase of system-level complexity. Scaling performance depends on more than transistor density. It comes down to how efficiently multiple compute dies, memory stacks, and interconnect fabrics operate as a single system. Designers are balancing performance, bandwidth, power, thermals, and manufacturability—simultaneously. Next-generation AI accelerators demand multi-terabyte-per-second memory bandwidth. Data movement consumes a growing share of total system power. Large monolithic dies face reticle limits, lower yields, and rising mask costs. Even traditional 2.5D approaches introduce interposer complexity, package size constraints, and limited flexibility for vertical integration. Alchip’s 3.5D ASIC platform addresses these challenges with a system-level approach to heterogeneous integration. It partitions large SoCs into optimized chiplets across multiple process nodes. Compute dies scale on leading-edge technologies, while I/O and memory functions remain on cost-efficient nodes to improve yield, reduces cost, and accelerates deployment. The platform combines horizontal chiplet scaling with selective vertical die stacking. This hybrid 3.5D architecture delivers higher interconnect density and significantly greater design flexibility than conventional approaches. Alchip integrates this architecture with advanced packaging technologies including CoWoS-S, CoWoS-R, CoWoS-L, and TSMC-SoIC-X. The result is high-bandwidth, low-latency die-to-die connectivity that supports multi-terabyte-per-second aggregate throughput. The platform is currently delivering up to 3–5x higher interconnect density using 30-40% less energy per bit at a lower latency of up to 35%. The platform co-designs die placement, heat dissipation, and power delivery to improve efficiency. Shorter vertical power paths and optimized power delivery networks enhance performance. Integrated thermal strategies support advanced data center cooling approaches. The 3DIC platform also provides a unified design and integration flow across silicon, packaging, and system layers. This reduces development friction and allows designers to focus on workload optimization rather than infrastructure integration. Alchip’s 3DIC platform is ideal for hyperscale cloud providers, AI accelerator startups, and HPC system companies developing custom silicon. A typical configuration may include multiple compute chiplets on advanced nodes, I/O dies on mature nodes, and HBM stacks within a single package. Systems are now reaching multi-kilowatts powers levels. The ASIC platform extends the company’s long-standing leadership in advanced-node ASIC design and 2.5D/3DIC integration.お知らせ • Mar 09Alchip Technologies, Limited, Annual General Meeting, May 26, 2026Alchip Technologies, Limited, Annual General Meeting, May 26, 2026. Location: 3 floor no,168, ching yeh 4th rd., jhongshan district, taipei city Taiwanお知らせ • Sep 04Alchip 3DIC Test Chip Tape Out Validates Ecosystem ReadinessAlchip Technologies validated its 3DIC ecosystem readiness with results from its 3DIC test chip tape out. The results vaulted Alchip into a clear 3DIC technology leadership because it validated an entire, integrated 3DIC solution, as well as its various elements. The test chip provided CPU/NPU core demonstration, UCIe and PCIe PHY preparation, Lite-IO infrastructure, and third-party IP. The latter is particularly important because any 3DIC proven IP is hard to find. Alchip's 3DIC test chip success holds greater than normal implications because it provided technical validation of the company's 3DIC ecosystem. Alchip's growing ASIC ecosystem assures AI and HPC developers of a fast time-to-design, accurate pathway for highly complex ASIC devices. Alchip's ecosystem encompasses a technology-specific design flow, package design flow, die-to-die IP, and interconnect. Tape out validation is a critical step because 3DIC elements differ significantly from their 2D counterparts. Alchip's device integrates a 3nm top die and a 5nm base die, assembled using TSMC's SoIC®?-X packaging technology. It is designed to stress test power density and thermal dissipation challenges inherent in 3D integration. The results also inform future 3DIC designs incorporating 2nm and 3nm stacked chiplets. The chip includes a CPU, NPU core and high-power logic on the top die. The base die integrates a network-on-chip, L3 cache, and interface IP. The two dies are connected using APLink-3D Lite IO. The tape out validated several critical 3DIC capabilities, including: Cross-die synchronous die-to-die IP. Design-for-test strategies with redundancy, repair, and process monitoring. Signal and power integrity analysis for 3D stacking. Thermal and mechanical simulations for vertical integration. 3D physical design implementation and verification. The dual-die design required a new approach to physical and logical integration. The EDA tools and design methods were updated to support co-design across both dies. Sign-off included electrical, timing, and mechanical integrity across the full 3D assembly. The company tested Interface IP, architected specifically for 3DIC. Interoperability and full functionality requested new IP. Each die, especially the bottom die, requires custom PHY implementations for protocols such as UCIe, and PCIe. 3DI/O timing represents another major advancement. Alchip has limited die-to-die latency to 40 picoseconds, enabling timing paths that span dies without degrading performance. A fully integrated 3D clocking structure ensure coherent operation across both layers with minimal timing skew. Four IP vendors participated in the test chip program. Two contributed proven hard macros. Two others evaluated new IP on the test platform. An EDA flow vendor collaborated to ensure tool and methodology readiness.お知らせ • Jul 22Alchip Technologies, Limited Introduces 2nm Design PlatformAlchip Technologies, Limited has received the first wafers from its 2nm Design Platform and is actively engaged with customers on high performance 2nm ASIC development. The new 2nm Design Platform facilitates the physical design of a 2nm chip using multiple types of 2.5D/3D technologies. It supports the development of 5nm or 3nm IO chiplets that work in conjunction with 2nm compute dies. The complete physical design methodology supports technology up to 2nm, and advanced packaging including CoWoS®?-S/R/L 2.5D/3D/3D package, System on Integrated Chips (TSMC-SoIC®?-X), die-to-die IP, and IO chiplet design. System on Wafer (TSMC-SoW™?) 3DIC solutions are on track to be supported as well. The 2nm process node introduces a complex layout structure, with a significantly greater variety of standard cells that make placement and signal/power routing more challenging. Alchip's design methodology reduces turnaround time in both design implementation and verification by proactively addressing all side effects before floor planning and clock/power planning stages. From a packaging standpoint, power density and thermal dissipation per mm2 at the 2nm node are higher because of a larger gate count and faster operating speed. While 2nm IO chiplets are not yet available, Alchip's 2nm Design Platform provides the more practical approach, enabling 2nm compute dies to work seamlessly with 3nm or 5nm IO chiplets. Alchip's 2nm test chip achieved first-pass silicon success, reinforcing the company's high-performance ASIC leadership. The chip successfully integrated Alchip's AP-Link-3D I/O IP, demonstrating its readiness for 3D SoIC-X chiplet applications. The results also lay a foundation for the company's migration to TSMC's A16™? process node.お知らせ • May 30Alchip Technologies, Limited Approves the Election of DirectorsAlchip Technologies, Limited at its AGM held on May 29, 2025, approved the election of Directors: Herbert Chang and Independent Directors: Andrew Kuo, Jerry Tzou, Derek C.Y. Tien and Saria Tseng.最新情報をもっと見るRecent updatesお知らせ • Apr 21Alchip Technologies Announces Appointment of Freddy Engineer as Chief Business Officer of Alchip North AmericaAlchip Technologies announced the appointment of Mr. Freddy Engineer as Chief Business Officer (CBO) and General Manager of Alchip North America. In this role, Mr. Engineer will lead the company’s global business growth strategy while accelerating expansion of the U.S. market. Mr. Engineer will oversee worldwide sales and lead the North America Business Unit. His mandate includes expanding customer relationships, strengthening go-to-market execution, and aligning global teams to support the growing demand for the company’s high-performance custom ASIC solutions. Mr. Engineer brings more than two decades of leadership experience across the data center, communications, and cloud infrastructure markets. Most recently, he served as GM of the Semi-Custom Silicon Business at NVIDIA, where he led global business development initiatives for cloud service providers, hyperscalers, and communications customers. Prior to NVIDIA, he spent approximately 25 years at Xilinx Inc. holding several senior leadership positions, including Corporate Vice President and General Manager of the Data Center Business. During his tenure, Mr. Engineer built and scaled Xilinx’s data center organization, strengthening strategic partnerships with Tier-1 hyperscalers and other key customers. Mr. Engineer’s background in global sales, strategic accounts, and field applications engineering positions him to bridge technology strategy with customer needs as demand for Alchip’s ASIC from AI and data center enterprises continues to scale.お知らせ • Apr 17Alchip Technologies Announces 3Dic Platform for Next-Generation Ai ProcessorsAlchip Technologies said its 3DIC platform is driving more efficient development of next-generation AI and high-performance computing devices through flexible chiplet architectures and advanced packaging integration. AI infrastructure is in a new phase of system-level complexity. Scaling performance depends on more than transistor density. It comes down to how efficiently multiple compute dies, memory stacks, and interconnect fabrics operate as a single system. Designers are balancing performance, bandwidth, power, thermals, and manufacturability—simultaneously. Next-generation AI accelerators demand multi-terabyte-per-second memory bandwidth. Data movement consumes a growing share of total system power. Large monolithic dies face reticle limits, lower yields, and rising mask costs. Even traditional 2.5D approaches introduce interposer complexity, package size constraints, and limited flexibility for vertical integration. Alchip’s 3.5D ASIC platform addresses these challenges with a system-level approach to heterogeneous integration. It partitions large SoCs into optimized chiplets across multiple process nodes. Compute dies scale on leading-edge technologies, while I/O and memory functions remain on cost-efficient nodes to improve yield, reduces cost, and accelerates deployment. The platform combines horizontal chiplet scaling with selective vertical die stacking. This hybrid 3.5D architecture delivers higher interconnect density and significantly greater design flexibility than conventional approaches. Alchip integrates this architecture with advanced packaging technologies including CoWoS-S, CoWoS-R, CoWoS-L, and TSMC-SoIC-X. The result is high-bandwidth, low-latency die-to-die connectivity that supports multi-terabyte-per-second aggregate throughput. The platform is currently delivering up to 3–5x higher interconnect density using 30-40% less energy per bit at a lower latency of up to 35%. The platform co-designs die placement, heat dissipation, and power delivery to improve efficiency. Shorter vertical power paths and optimized power delivery networks enhance performance. Integrated thermal strategies support advanced data center cooling approaches. The 3DIC platform also provides a unified design and integration flow across silicon, packaging, and system layers. This reduces development friction and allows designers to focus on workload optimization rather than infrastructure integration. Alchip’s 3DIC platform is ideal for hyperscale cloud providers, AI accelerator startups, and HPC system companies developing custom silicon. A typical configuration may include multiple compute chiplets on advanced nodes, I/O dies on mature nodes, and HBM stacks within a single package. Systems are now reaching multi-kilowatts powers levels. The ASIC platform extends the company’s long-standing leadership in advanced-node ASIC design and 2.5D/3DIC integration.お知らせ • Mar 09Alchip Technologies, Limited, Annual General Meeting, May 26, 2026Alchip Technologies, Limited, Annual General Meeting, May 26, 2026. Location: 3 floor no,168, ching yeh 4th rd., jhongshan district, taipei city Taiwanお知らせ • Sep 04Alchip 3DIC Test Chip Tape Out Validates Ecosystem ReadinessAlchip Technologies validated its 3DIC ecosystem readiness with results from its 3DIC test chip tape out. The results vaulted Alchip into a clear 3DIC technology leadership because it validated an entire, integrated 3DIC solution, as well as its various elements. The test chip provided CPU/NPU core demonstration, UCIe and PCIe PHY preparation, Lite-IO infrastructure, and third-party IP. The latter is particularly important because any 3DIC proven IP is hard to find. Alchip's 3DIC test chip success holds greater than normal implications because it provided technical validation of the company's 3DIC ecosystem. Alchip's growing ASIC ecosystem assures AI and HPC developers of a fast time-to-design, accurate pathway for highly complex ASIC devices. Alchip's ecosystem encompasses a technology-specific design flow, package design flow, die-to-die IP, and interconnect. Tape out validation is a critical step because 3DIC elements differ significantly from their 2D counterparts. Alchip's device integrates a 3nm top die and a 5nm base die, assembled using TSMC's SoIC®?-X packaging technology. It is designed to stress test power density and thermal dissipation challenges inherent in 3D integration. The results also inform future 3DIC designs incorporating 2nm and 3nm stacked chiplets. The chip includes a CPU, NPU core and high-power logic on the top die. The base die integrates a network-on-chip, L3 cache, and interface IP. The two dies are connected using APLink-3D Lite IO. The tape out validated several critical 3DIC capabilities, including: Cross-die synchronous die-to-die IP. Design-for-test strategies with redundancy, repair, and process monitoring. Signal and power integrity analysis for 3D stacking. Thermal and mechanical simulations for vertical integration. 3D physical design implementation and verification. The dual-die design required a new approach to physical and logical integration. The EDA tools and design methods were updated to support co-design across both dies. Sign-off included electrical, timing, and mechanical integrity across the full 3D assembly. The company tested Interface IP, architected specifically for 3DIC. Interoperability and full functionality requested new IP. Each die, especially the bottom die, requires custom PHY implementations for protocols such as UCIe, and PCIe. 3DI/O timing represents another major advancement. Alchip has limited die-to-die latency to 40 picoseconds, enabling timing paths that span dies without degrading performance. A fully integrated 3D clocking structure ensure coherent operation across both layers with minimal timing skew. Four IP vendors participated in the test chip program. Two contributed proven hard macros. Two others evaluated new IP on the test platform. An EDA flow vendor collaborated to ensure tool and methodology readiness.お知らせ • Jul 22Alchip Technologies, Limited Introduces 2nm Design PlatformAlchip Technologies, Limited has received the first wafers from its 2nm Design Platform and is actively engaged with customers on high performance 2nm ASIC development. The new 2nm Design Platform facilitates the physical design of a 2nm chip using multiple types of 2.5D/3D technologies. It supports the development of 5nm or 3nm IO chiplets that work in conjunction with 2nm compute dies. The complete physical design methodology supports technology up to 2nm, and advanced packaging including CoWoS®?-S/R/L 2.5D/3D/3D package, System on Integrated Chips (TSMC-SoIC®?-X), die-to-die IP, and IO chiplet design. System on Wafer (TSMC-SoW™?) 3DIC solutions are on track to be supported as well. The 2nm process node introduces a complex layout structure, with a significantly greater variety of standard cells that make placement and signal/power routing more challenging. Alchip's design methodology reduces turnaround time in both design implementation and verification by proactively addressing all side effects before floor planning and clock/power planning stages. From a packaging standpoint, power density and thermal dissipation per mm2 at the 2nm node are higher because of a larger gate count and faster operating speed. While 2nm IO chiplets are not yet available, Alchip's 2nm Design Platform provides the more practical approach, enabling 2nm compute dies to work seamlessly with 3nm or 5nm IO chiplets. Alchip's 2nm test chip achieved first-pass silicon success, reinforcing the company's high-performance ASIC leadership. The chip successfully integrated Alchip's AP-Link-3D I/O IP, demonstrating its readiness for 3D SoIC-X chiplet applications. The results also lay a foundation for the company's migration to TSMC's A16™? process node.お知らせ • May 30Alchip Technologies, Limited Approves the Election of DirectorsAlchip Technologies, Limited at its AGM held on May 29, 2025, approved the election of Directors: Herbert Chang and Independent Directors: Andrew Kuo, Jerry Tzou, Derek C.Y. Tien and Saria Tseng.お知らせ • May 01Alchip Technologies, Limited to Report Q1, 2025 Results on May 09, 2025Alchip Technologies, Limited announced that they will report Q1, 2025 results on May 09, 2025お知らせ • Mar 03Alchip Technologies, Limited, Annual General Meeting, May 29, 2025Alchip Technologies, Limited, Annual General Meeting, May 29, 2025. Location: 3 floor no,168, ching yeh 4th rd., jhongshan district, taipei city Taiwanお知らせ • Mar 01Alchip Technologies, Limited Proposes Dividend Distribution for the Period from January 1, 2024 to December 31, 2024The Board of Directors of Alchip Technologies, Limited Proposed Dividend Distribution for the period from January 1, 2024 to December 31, 2024. Appropriations of earnings in cash dividends to shareholders TWD 40.05 per share. Total amount of cash distributed to shareholders TWD 3,232,587,572.お知らせ • Feb 20Alchip Technologies, Limited to Report Q4, 2024 Results on Feb 27, 2025Alchip Technologies, Limited announced that they will report Q4, 2024 results on Feb 27, 2025お知らせ • Nov 06Alchip Reveals 2Nm Test Chip PlanAlchip Technologies reported that it has taped out a 2nm test chip and expects the results by the first quarter of next year. It also announced that it is actively engaged with customers on high performance 2nm ASIC development. The two revelations put Alchip among the first wave of IC innovators to successfully adopted the revolutionary gate all-around transistor architecture. The test chip features high-speed SRAM and automatic place-and-route design to ensure optimal performance. It also includes silicon performance monitors for real-time insights and integrates Alchip's Lite I/O with shared and non-shared power domains, positioning it to handle 3DIC options. The test chip will establish the design flow and methodology for the latest gate all-around and nanosheet transistor structures. It will also generate power, performance, and area data from the 2nm process technology. Alchip taped out its test chip in September and sees it as a critical step in maintaining its high-performance ASIC advanced technology leadership, because the results will help the company prepare for its future migration to the A16 manufacturing. Although it's a monolithic design, the Alchip's 2nm test chip integrates and validates the company's AP-Link-3D I/O IP for potential use in future 3D-SoIC-X chiplets.お知らせ • Nov 02Alchip Technologies, Limited Announces the Establishment of the First Nomination CommitteeAlchip Technologies, Limited announced the establishment of the first Nomination Committee of the company. Name of the new position holder: Johnny Shyang-Lin Shen, The CEO of the Company. Mao-Wei Hung, Professor, Department of International Business, National Taiwan University. Brian Chiang, Managing Director of Walden International Taiwan Co. Ltd. Effective date of the new member: November 1, 2024. The committee convener is Mr. Mao-Wei Hung.お知らせ • Oct 25Alchip Technologies, Limited to Report Q3, 2024 Results on Nov 01, 2024Alchip Technologies, Limited announced that they will report Q3, 2024 results on Nov 01, 2024お知らせ • Oct 17Alchip Technologies, Limited Reveals 3DIC Design Optimization KeysAlchip Technologies, Limited has revealed that it has optimized 3DIC designs by overcoming four critical challenges. The announcement came through a technical presentation at the 2024 TSMC Open Innovation Platform (OIP) Ecosystem Forum. The paper, "Efficient 3D Chiplet Stacking Using TSMC-SoIC," describes how Alchip used a third-party EDA tool to overcome four complex technical challenges. In the paper, Erez Shaizaf, Alchip's Chief Technical Officer, identifies three major barriers to 3DIC success: power delivery, dies electrical interconnect, and system-wide thermal challenges. He points out that power delivery really encompasses three separate challenges: power integrity, power grid design (including through silicon via distribution), and power integrity simulation and sign-off. Dies electrical interconnect are identified as low clock skew across dies, process variation immunity, noise immunity, data transmission across different power domains, inter-die setup/hold timing margin, PPA optimized IO cells for clock and data, and redundancy strategy. The paper details thermal challenges as 3DIC thermal characterization covering increased power density, 3D non-uniform power mapping, 3D thermal crosstalk effects, package, and system cooling solution modeling.お知らせ • Aug 24Alchip Technologies, Limited Announces Cash Dividend, Payable on October 16, 2024Alchip Technologies, Limited announced cash dividend of Common share is USD 56,300,842. The Chairman was authorized by the Board to adjust the dividend payout ratio. The actual dividend should be subject to the exchange rate of conversion upon the receipt of the dividend by the Company’s stock agent. The cash dividend will round down to the nearest Taiwan Dollar. The total amount of round down from the shareholders will be counted as the other income of the Company. Ex-rights (ex-dividend) trading date: September 12, 2024. Ex-rights (ex-dividend) record date: September 20, 2024. Payment date of common stock cash dividend distribution: October 16, 2024.お知らせ • Aug 16Alchip Technologies, Limited to Report Q2, 2024 Results on Aug 23, 2024Alchip Technologies, Limited announced that they will report Q2, 2024 results on Aug 23, 2024お知らせ • May 16Alchip Technologies, Limited announced that it expects to receive funding from Amazon.com, Inc.Alchip Technologies, Limited announced a private placement that it will issue 224,537 common shares to receive funding on May 14, 2024. The transaction will include participation from new investor, Amazon.com, Inc. The transaction has been approved by the board of directors of the company.お知らせ • Apr 28Alchip Technologies, Limited to Report Q1, 2024 Results on May 03, 2024Alchip Technologies, Limited announced that they will report Q1, 2024 results on May 03, 2024お知らせ • Apr 12Alchip Technologies Showcases High-Performance Computing Successes at CDNLiveAlchip Technologies Ltd. will exhibit at Cadence CDNLive on April 17th 2024. The company will demonstrate its advanced technology, advanced packaging, and chiplet design capabilities. At its booth, Alchip will demonstrate ASIC-industry leading high-performance computing design and artificial intelligence expertise, which accounts for 85% of its revenue. Alchip 5nm designs is in mass production and the company is currently enabling 4nm and 3nm designs, while actively readying their 2nm capabilities. Alchip will also discuss its successfully produced CoWoS®? device with 3nm and high-bandwidth memory capabilities. The company has successfully completed complex CoWoS-S and CoWos-R designs in multiple ongoing programs, with proven mass production of advanced CoWoS and MCM packages. Across the board, Alchip has developed an enviable track record of right-the-first-time, success. It has gone to mass production on a high power chiplet design that operates at 800W and features a 3x reticle interposer. Alchip has also executed a full reticle size design (>800mm2) at leading edge FinFET nodes, and one of the CoWoS packages (70x80mm2) in production.お知らせ • Mar 02+ 1 more updateAlchip Technologies, Limited, Annual General Meeting, May 30, 2024Alchip Technologies, Limited, Annual General Meeting, May 30, 2024. Location: 3F,No.168,Jingye 4th Rd. Zhongshan Dist., (Grand Victoria Hotel) Taipei City Taiwan Agenda: To consider The Business Report of 2023; Audit committee's Review Report on 2023 Consolidated Financial Statements; The Distribution of Bonus to Employees and Directors of the Company; 2023 Private Placement of Common Shares Processing Status Report; and to discuss other matters.お知らせ • Jan 18Alchip Technologies, Limited has filed a Follow-on Equity Offering in the amount of TWD 12.95 billion.Alchip Technologies, Limited has filed a Follow-on Equity Offering in the amount of TWD 12.95 billion. Security Name: Global Depositary Receipts Security Type: Depositary Receipt (Common Stock) Securities Offered: 3,700,000 Price\Range: TWD 3500お知らせ • Dec 14Alchip Unveils AI 3Dic Design and IP PlatformAlchip Technologies revealed that the company presented a paper at the TSMC 2023 Taiwan Open Innovation Platform®?Ecosystem Forum showcasing its ground-breaking collaborative advanced artificial intelligence (AI) 3DIC chiplet design and integrated IP methodology. Their revolutionary platform focuses on dramatically increasing the computational power required to handle complex neural networks and large datasets. Traditional architectures struggle to efficiently meet these requirements. But now, advanced SerDes IP technology enables larger scale with 2.5D and 3D package interconnection that consumes less power, occupies a smaller footprint, and operates with greater efficiency. 3DIC integration stores larger, more complex neural networks directly on one chiplet, reducing frequent data transfers to external memory, according to the paper. This enhances computational efficiency, reduces energy consumption, and enables real-time processing of larger datasets. The 3DIC technology stacks compute dies on top of memory and interconnect dies using high-density through-silicon-vias (TSV) and hyper bumps to increase compute transistor density, larger SRAM die, shorter interconnects, improved power efficiency with minimal latency, the authors said. The paper envisions combining IP-driven interconnects with 3DIC chiplets to address daunting challenges computational power, memory capacity, and interconnect optimization challenges. AI chip designers are now freed to push the boundaries of AI capabilities, leading to more powerful, efficient, and scalable artificial intelligence systems. Alchip revealed in the presentation that they designed the 3DIC device using TSMC's CoWoS®? advanced packaging to integrate the advanced SerDes IP. The package design has undergone thorough simulation for signal integrity (SI), power integrity (PI), and thermal considerations. A third-party user provided guidance on package breakout, thermal management, and PI consideration and have successfully completed a comprehensive system design, the paper announced.お知らせ • Nov 23Alchip Unveils First Automotive ASIC Design PlatformAlchip Technologies, Limited rolled out the semiconductor industry’s first Automotive ASIC platform at the Design Solutions Forum 2023. The platform targets the specialized needs of the global automotive industry. The Automotive platform streamlines the ASIC design needs of global automotive IC module and component manufacturers, as well as automotive companies themselves. Alchip saw significant pre-announcement interest from companies across Europe, Japan, the United States and Asia. The platform consists of six modules: Design for Autonomous Driving (AD)/Advanced Driver Assistance System (ADAS), Design for Safety, Design for Test, Design for Reliability, Automotive Chip Sign-off, and Automotive Chip Manufacturing (MFG) Service. Design for AD/ADAS is the platform’s starting point. Its Ultra-scale design capabilities integrates Central Processing Unit (CPU) and Neural Processing Unit (NPU) into the smallest possible die size, while meeting aggressive higher performance and lower power consumption required by automotive applications. The Design for Safety module follows the ISO26262 pre-scribed flow that includes required isolated TMR/Lock-Step design methodology. The module also features an experienced safety manager and includes the mandated Development Interface Agreement (DIA) that defines the relationship between the manufacturer and the supplier throughout the entire automotive safety lifecycle and activities. Design for Reliability includes enhanced Electromigration (EM) as part of silicon lifecycle management. It also covers AEC-Q grade IP sourcing and implementation. The Automotive Chip Manufacturing Service works with IATF16949 approved manufacturing suppliers. Services include tri-temp testing by target AEC-Q grade, automotive wafer, automotive substrate, assembly and burn-in. Design for Test capabilities support In System Test (IST) and MBIST/LBIST design, critical and redundancy logic for yield harvest, automotive-level ATPG coverage, and physical-aware ATPG. The final sign-off module covers an aging library based on a customer mission profile, OD/UD/AVS/DVFS library support, and the final Design for Manufacturing sign-off.お知らせ • Aug 23Alchip Technologies, Limited Announces Cash Dividend for 2023Alchip Technologies, Limited announced cash dividend per share of Common share is TWD 12.92 for 2023. The cash dividend of Common share is USD 30,268,787. The dividend per share is based on the total number of outstanding shares which are 74,077,185 as of August 18, 2023 and the foreign exchange rate which is based on the spot rate(TWD 31.97) set by the Bank of Taiwan on August 21, 2023. The cash dividend per share is TWD 13.06330849. The actual dividend should be subject to the exchange rate of conversion upon the receipt of the dividend by the Company's stock agent.お知らせ • Jun 27Alchip Technologies, Limited announced that it expects to receive TWD 999.12 million in funding from Wistron CorporationAlchip Technologies, Limited announced a private placement of 690,000 shares at an issue price of TWD 1,448 per share for proceeds of TWD 999,120,000 on June 26, 2023. The transaction will include participation from new investor Wistron Corporation.お知らせ • Feb 02Alchip Technologies Announces 3DFabric Alliance Support PlansAlchip Technologies is putting teeth into its role as a founding member of TSMC’s 3DFabric Alliance by enhancing its 3nm process technology and advanced packaging capabilities. The company supports the foundry initiative, announced in late October, seeing it as a market driver that will deliver Alchip’s most advanced high-performance computing ASIC technology to leading edge customer applications. TSMC’s 3DFabric is a comprehensive family of 3D silicon stacking and advanced packaging technologies that unleash customer’s innovation in system level approach. It consists of TSMC’s frontend technologies or TSMC-SoIC (System on Integrated Chips), dedicated fabs for 3D stacked dies’ assembling and testing, and TSMC 3DFabric’s backend technologies include CoWoS and InFO family of packaging technologies. The TSMC 3DFabric Alliance is the latest addition to TSMC’s Open Innovation Platform (OIP). The new alliance partners have early access to TSMC’s 3DFabric technologies, enabling them to develop and optimize their solutions in parallel with TSMC. This gives customers early availability to EDA, IP, memory, outsourced semiconductor assembly and test (OSAT), substrate, and testing. Alchip has been taking 3nm customer ASIC designs and tapeout its first test chip in January 2023. It became the first dedicated high-performance ASIC company to announce total design and production ecosystem readiness targeting TSMC’s latest N3E process technology. On the advanced packaging front, Alchip is fine tuning its industry leading chip-on-safer-on-substrate (CoWoS) packaging capability. CoWoS improves overall chip interconnect density and performance and is critical to nearly every high-performance computing (HPC) ASIC. CoWoS is a 2.5D wafer-level multi-chip packaging technology that incorporates side-by-side die on a silicon interposer. Micro-bumps bond individual chips to a silicon interposer, forming a chip-on-wafer. Packaging is completed by bonding to a package substrate. CoWoS chiplet sets include a high-performance system-on-a-chip (SoC) and a high-performance memory (HBM3 or HBM2E) block. Alchip’s CoWoS service covers all CoWoS package types such as CoWoS-S, CoWoS-R and CoWoS-L.お知らせ • Nov 05Alchip Technologies, Limited Announces Appointment of Daniel Wang as Corporate Governance Officer, with Effect from November 4, 2022Alchip Technologies, Limited announced appointment of Daniel Wang as Corporate Governance Officer, with effect from November 4, 2022. Daniel Wang is the CFO of the company.お知らせ • Nov 04Alchip Technologies, Limited to Report Q3, 2022 Results on Nov 04, 2022Alchip Technologies, Limited announced that they will report Q3, 2022 results at 2:30 PM, Taipei Standard Time on Nov 04, 2022お知らせ • Aug 27Alchip Technologies, Limited Announces Cash DividendThe board of Alchip Technologies, Limited the cash dividend of Common share is USD 26,772,486. The Chairman was authorized by the Board to adjust the dividend payout ratio. The actual dividend should be subject to the exchange rate of conversion upon the receipt of the dividend by the Company¡y's stock agent. Ex-rights (ex-dividend) trading date is September 18, 2022. Ex-rights (ex-dividend) record date is September 24, 2022.お知らせ • Jun 22Alchip Technologies, Limited Announces Change of Accounting OfficerAlchip Technologies, Limited appointed Yuki Jin, Financial Controller of China region as Accounting officer in place of Nancy Chan, Financial Controller. Effective date: June 20, 2022.お知らせ • Jun 16Alchip Technologies Offers 3nm ASIC Design ServicesAlchip Technologies announced that its high-performance computing ASIC services are now taking 3nm designs and targeting its first test chip for first quarter 2023. The company will unveil its chiplet technology at the TSMC North America Technology Symposium on June 16. Alchip becomes the first dedicated high-performance ASIC company to announce total design readiness of their design and production ecosystem. The new service targets TSMC’s latest N3E process technology. The company revealed that it completed its design technology and infrastructure during the current quarter and will make available its design methodology within a couple of weeks. Other assets in place include a complete library of best-in-class 3rd party IP covering DDR5, GDDR6, HBM2E, HBM3, PCIe5, and 112G SERDES IP from Tier 1 providers. 4nm Test Chip Tape-out Next Quarter: Alchip also revealed that its first 4nm test chip, targeting TSMC’s N4P process technology will be taped out early in August. Design methodology, design technology and infrastructure and test chips specification had all been finalized at the end of last year. APLink 4.0 supports N5/N4P die-to-die connection for advanced packaging designs. Alchip is traded on the Taiwan Stock Exchange, with Global Repository Receipts trading on the Luxembourg Exchange.お知らせ • Jun 11Alchip Technologies, Limited Approves the Appointment of Herbert Chang as DirectorAlchip Technologies, Limited at its AGM held on June 10, 2022, approved the appointment of Herbert Chang as Director.お知らせ • May 12Alchip Technologies, Limited Reaffirms Revenue Guidance for the Year 2022Alchip Technologies, Limited reaffirmed revenue guidance for the year 2022. The company left unchanged its forecast for another promising revenue growth in 2022.お知らせ • Mar 07+ 1 more updateAlchip Technologies, Limited Announces Personnel Change of GM of US Business UnitAlchip Technologies, Limited announced personnel change of GM of US Business Unit. Name, title, and resume of the previous position holder: Hiroyuki Nagashima and Name, title, and resume of the new position holder: Yaw-Lin Hwang, Effective date is March 4, 2022.お知らせ • Mar 06+ 1 more updateAlchip Technologies, Limited Proposes Cash Dividends for the Year Ended December 31, 2021Alchip Technologies, Limited proposed cash dividends to shareholders of TWD 10.59 per share for the year ended December 31, 2021. Total amount of cash distributed to shareholders of TWD 751,235,956.お知らせ • Mar 06Alchip Technologies, Limited, Annual General Meeting, Jun 11, 2021Alchip Technologies, Limited, Annual General Meeting, Jun 11, 2021. Location: 3F,No.168,Jingye 4th Rd. Zhongshan Dist Grand Victoria Hotel Taipei County Taiwan Agenda: To consider the business report of 2020; to consider audit committee's Review Report on 2020 Consolidated Financial Statements; to consider the distribution of Bonus to Employees and Directors of the Company; to consider amendments to the Memorandum and Articles of Association of the Company; to consider amendments to the Rules of Procedure for Shareholders Meetings of the Company; and to consider other matters.お知らせ • Feb 05Alchip Technologies, Limited Unveils Two Sign-Off Verification Options to Accommodate Both Design Economics and Enhanced Yield ObjectivesAlchip Technologies, Limited revealed that demand for post-GDSII backend services has increased exponentially across all high-performance computing ASIC applications. The company is meeting this uptick with invested emphasis on production, packaging and test and assembly services. As a result, Alchip's post-GDSII services are experiencing high demand as systems and OEM companies face both technology challenges and engineering talent limitations associated with traditional backend services. Sophisticated high-performance frontend design resources are expensive and, depending on geographic location, somewhat scarce. The result is an uptick in companies outsourcing production, packaging, test and assembly responsibilities to ASIC companies who are far more experienced in these strategic areas. Alchip has elevated its packaging capabilities to include Chip-on-Wafer-on-Substrate (CoWoS®) first developed by TSMC and this spring is expected to announced a true 2.5D INFO capability. Alchip's CoWoS process runs on dedicated tooling and demonstrates IP performance equivalent to that of an original design. The process also includes online debugging and active thermal control. The company's in-house design substrate design capabilities assure compliance with all system requirements and establishes the frame work for critical foundry-to-final test flow. The company has also unveiled a two sign-off verification options to accommodate both design economics and enhanced yield objectives. Standard sign-off verification includes DRC/LVS/ERC checks that guard against fatal manufacturing error. A second design options calls for additional focus on Electrical, DFT, STA and/or clock verification, depending on specific customer requirements.株主還元ALCHALU SemiconductorLU 市場7D6.8%0%0%1Y57.6%0%0%株主還元を見る業界別リターン: ALCHA過去 1 年間で125.7 % の収益を上げたLuxembourg Semiconductor業界を下回りました。リターン対市場: ALCHA過去 1 年間で20 % の収益を上げたLuxembourg市場を上回りました。価格変動Is ALCHA's price volatile compared to industry and market?ALCHA volatilityALCHA Average Weekly Movement11.0%Semiconductor Industry Average Movement0%Market Average Movement0%10% most volatile stocks in LU Market0%10% least volatile stocks in LU Market0%安定した株価: ALCHAの株価は、 Luxembourg市場と比較して過去 3 か月間で変動しています。時間の経過による変動: ALCHAの weekly volatility ( 11% ) は過去 1 年間安定していますが、依然としてLuxembourgの株式の 75% よりも高くなっています。会社概要設立従業員CEO（最高経営責任者ウェブサイト1992n/aJohnny Shenwww.alchip.comアルチップ・テクノロジーズ社は、子会社とともに、日本、台湾、中国において、ファブレス特定用途向け集積回路（ASIC）およびシステムオンチップ（SOC）の研究開発、設計、製造を行っています。同社は、SoCフロントエンド設計、フィジカル・バックエンド設計、低消費電力、高性能、テスタビリティ設計、先進パッケージ・ソリューションなどのASIC設計サービス、生産サービス、先進パッケージ、先進テスト、製品エンジニアリング、品質保証サービス、インテグレーションや認証などのIPサービスを提供している。同社の製品は、AI、HPC、HDTV、DSC、携帯電話、娯楽機器、ネットワーク/通信機器、その他の電子製品に使用されています。アルチップ・テクノロジーズ社は2002年に設立され、台湾台北市に本社を置いています。もっと見るAlchip Technologies, Limited 基礎のまとめAlchip Technologies の収益と売上を時価総額と比較するとどうか。ALCHA 基礎統計学時価総額US$12.68b収益（TTM）US$176.76m売上高(TTM)US$782.59m71.7xPER（株価収益率16.2xP/SレシオALCHA は割高か？公正価値と評価分析を参照収益と収入最新の決算報告書（TTM）に基づく主な収益性統計ALCHA 損益計算書（TTM）収益NT$24.63b売上原価NT$16.80b売上総利益NT$7.83bその他の費用NT$2.26b収益NT$5.56b直近の収益報告Mar 31, 2026次回決算日該当なし一株当たり利益（EPS）68.23グロス・マージン31.78%純利益率22.59%有利子負債／自己資本比率0%ALCHA の長期的なパフォーマンスは？過去の実績と比較を見る配当金0.7%現在の配当利回り50%配当性向View Valuation企業分析と財務データの現状データ最終更新日（UTC時間）企業分析2026/05/22 13:56終値2026/05/22 00:00収益2026/03/31年間収益2025/12/31データソース企業分析に使用したデータはS&P Global Market Intelligence LLC のものです。本レポートを作成するための分析モデルでは、以下のデータを使用しています。データは正規化されているため、ソースが利用可能になるまでに時間がかかる場合があります。パッケージデータタイムフレーム米国ソース例会社財務10年損益計算書キャッシュ・フロー計算書貸借対照表SECフォーム10-KSECフォーム10-Qアナリストのコンセンサス予想+プラス3年予想財務アナリストの目標株価アナリストリサーチレポートBlue Matrix市場価格30年株価配当、分割、措置ICEマーケットデータSECフォームS-1所有権10年トップ株主インサイダー取引SECフォーム4SECフォーム13Dマネジメント10年リーダーシップ・チーム取締役会SECフォーム10-KSECフォームDEF 14A主な進展10年会社からのお知らせSECフォーム8-K* 米国証券を対象とした例であり、非米国証券については、同等の規制書式および情報源を使用。特に断りのない限り、すべての財務データは1年ごとの期間に基づいていますが、四半期ごとに更新されます。これは、TTM（Trailing Twelve Month）またはLTM（Last Twelve Month）データとして知られています。詳細はこちら。分析モデルとスノーフレーク本レポートを生成するために使用した分析モデルの詳細は当社のGithubページでご覧いただけます。また、レポートの使用方法に関するガイドやYoutubeのチュートリアルも掲載しています。シンプリー・ウォールストリート分析モデルを設計・構築した世界トップクラスのチームについてご紹介します。業界およびセクターの指標私たちの業界とセクションの指標は、Simply Wall Stによって6時間ごとに計算されます。アナリスト筋Alchip Technologies, Limited 14 これらのアナリストのうち、弊社レポートのインプットとして使用した売上高または利益の予想を提出したのは、 。アナリストの投稿は一日中更新されます。22 アナリスト機関Haas LiuBofA Global ResearchLiyen ChenCapital Securities Corporationnull nullCapital Securities Corporation19 その他のアナリストを表示
お知らせ • Apr 21Alchip Technologies Announces Appointment of Freddy Engineer as Chief Business Officer of Alchip North AmericaAlchip Technologies announced the appointment of Mr. Freddy Engineer as Chief Business Officer (CBO) and General Manager of Alchip North America. In this role, Mr. Engineer will lead the company’s global business growth strategy while accelerating expansion of the U.S. market. Mr. Engineer will oversee worldwide sales and lead the North America Business Unit. His mandate includes expanding customer relationships, strengthening go-to-market execution, and aligning global teams to support the growing demand for the company’s high-performance custom ASIC solutions. Mr. Engineer brings more than two decades of leadership experience across the data center, communications, and cloud infrastructure markets. Most recently, he served as GM of the Semi-Custom Silicon Business at NVIDIA, where he led global business development initiatives for cloud service providers, hyperscalers, and communications customers. Prior to NVIDIA, he spent approximately 25 years at Xilinx Inc. holding several senior leadership positions, including Corporate Vice President and General Manager of the Data Center Business. During his tenure, Mr. Engineer built and scaled Xilinx’s data center organization, strengthening strategic partnerships with Tier-1 hyperscalers and other key customers. Mr. Engineer’s background in global sales, strategic accounts, and field applications engineering positions him to bridge technology strategy with customer needs as demand for Alchip’s ASIC from AI and data center enterprises continues to scale.
お知らせ • Apr 17Alchip Technologies Announces 3Dic Platform for Next-Generation Ai ProcessorsAlchip Technologies said its 3DIC platform is driving more efficient development of next-generation AI and high-performance computing devices through flexible chiplet architectures and advanced packaging integration. AI infrastructure is in a new phase of system-level complexity. Scaling performance depends on more than transistor density. It comes down to how efficiently multiple compute dies, memory stacks, and interconnect fabrics operate as a single system. Designers are balancing performance, bandwidth, power, thermals, and manufacturability—simultaneously. Next-generation AI accelerators demand multi-terabyte-per-second memory bandwidth. Data movement consumes a growing share of total system power. Large monolithic dies face reticle limits, lower yields, and rising mask costs. Even traditional 2.5D approaches introduce interposer complexity, package size constraints, and limited flexibility for vertical integration. Alchip’s 3.5D ASIC platform addresses these challenges with a system-level approach to heterogeneous integration. It partitions large SoCs into optimized chiplets across multiple process nodes. Compute dies scale on leading-edge technologies, while I/O and memory functions remain on cost-efficient nodes to improve yield, reduces cost, and accelerates deployment. The platform combines horizontal chiplet scaling with selective vertical die stacking. This hybrid 3.5D architecture delivers higher interconnect density and significantly greater design flexibility than conventional approaches. Alchip integrates this architecture with advanced packaging technologies including CoWoS-S, CoWoS-R, CoWoS-L, and TSMC-SoIC-X. The result is high-bandwidth, low-latency die-to-die connectivity that supports multi-terabyte-per-second aggregate throughput. The platform is currently delivering up to 3–5x higher interconnect density using 30-40% less energy per bit at a lower latency of up to 35%. The platform co-designs die placement, heat dissipation, and power delivery to improve efficiency. Shorter vertical power paths and optimized power delivery networks enhance performance. Integrated thermal strategies support advanced data center cooling approaches. The 3DIC platform also provides a unified design and integration flow across silicon, packaging, and system layers. This reduces development friction and allows designers to focus on workload optimization rather than infrastructure integration. Alchip’s 3DIC platform is ideal for hyperscale cloud providers, AI accelerator startups, and HPC system companies developing custom silicon. A typical configuration may include multiple compute chiplets on advanced nodes, I/O dies on mature nodes, and HBM stacks within a single package. Systems are now reaching multi-kilowatts powers levels. The ASIC platform extends the company’s long-standing leadership in advanced-node ASIC design and 2.5D/3DIC integration.
お知らせ • Mar 09Alchip Technologies, Limited, Annual General Meeting, May 26, 2026Alchip Technologies, Limited, Annual General Meeting, May 26, 2026. Location: 3 floor no,168, ching yeh 4th rd., jhongshan district, taipei city Taiwan
お知らせ • Sep 04Alchip 3DIC Test Chip Tape Out Validates Ecosystem ReadinessAlchip Technologies validated its 3DIC ecosystem readiness with results from its 3DIC test chip tape out. The results vaulted Alchip into a clear 3DIC technology leadership because it validated an entire, integrated 3DIC solution, as well as its various elements. The test chip provided CPU/NPU core demonstration, UCIe and PCIe PHY preparation, Lite-IO infrastructure, and third-party IP. The latter is particularly important because any 3DIC proven IP is hard to find. Alchip's 3DIC test chip success holds greater than normal implications because it provided technical validation of the company's 3DIC ecosystem. Alchip's growing ASIC ecosystem assures AI and HPC developers of a fast time-to-design, accurate pathway for highly complex ASIC devices. Alchip's ecosystem encompasses a technology-specific design flow, package design flow, die-to-die IP, and interconnect. Tape out validation is a critical step because 3DIC elements differ significantly from their 2D counterparts. Alchip's device integrates a 3nm top die and a 5nm base die, assembled using TSMC's SoIC®?-X packaging technology. It is designed to stress test power density and thermal dissipation challenges inherent in 3D integration. The results also inform future 3DIC designs incorporating 2nm and 3nm stacked chiplets. The chip includes a CPU, NPU core and high-power logic on the top die. The base die integrates a network-on-chip, L3 cache, and interface IP. The two dies are connected using APLink-3D Lite IO. The tape out validated several critical 3DIC capabilities, including: Cross-die synchronous die-to-die IP. Design-for-test strategies with redundancy, repair, and process monitoring. Signal and power integrity analysis for 3D stacking. Thermal and mechanical simulations for vertical integration. 3D physical design implementation and verification. The dual-die design required a new approach to physical and logical integration. The EDA tools and design methods were updated to support co-design across both dies. Sign-off included electrical, timing, and mechanical integrity across the full 3D assembly. The company tested Interface IP, architected specifically for 3DIC. Interoperability and full functionality requested new IP. Each die, especially the bottom die, requires custom PHY implementations for protocols such as UCIe, and PCIe. 3DI/O timing represents another major advancement. Alchip has limited die-to-die latency to 40 picoseconds, enabling timing paths that span dies without degrading performance. A fully integrated 3D clocking structure ensure coherent operation across both layers with minimal timing skew. Four IP vendors participated in the test chip program. Two contributed proven hard macros. Two others evaluated new IP on the test platform. An EDA flow vendor collaborated to ensure tool and methodology readiness.
お知らせ • Jul 22Alchip Technologies, Limited Introduces 2nm Design PlatformAlchip Technologies, Limited has received the first wafers from its 2nm Design Platform and is actively engaged with customers on high performance 2nm ASIC development. The new 2nm Design Platform facilitates the physical design of a 2nm chip using multiple types of 2.5D/3D technologies. It supports the development of 5nm or 3nm IO chiplets that work in conjunction with 2nm compute dies. The complete physical design methodology supports technology up to 2nm, and advanced packaging including CoWoS®?-S/R/L 2.5D/3D/3D package, System on Integrated Chips (TSMC-SoIC®?-X), die-to-die IP, and IO chiplet design. System on Wafer (TSMC-SoW™?) 3DIC solutions are on track to be supported as well. The 2nm process node introduces a complex layout structure, with a significantly greater variety of standard cells that make placement and signal/power routing more challenging. Alchip's design methodology reduces turnaround time in both design implementation and verification by proactively addressing all side effects before floor planning and clock/power planning stages. From a packaging standpoint, power density and thermal dissipation per mm2 at the 2nm node are higher because of a larger gate count and faster operating speed. While 2nm IO chiplets are not yet available, Alchip's 2nm Design Platform provides the more practical approach, enabling 2nm compute dies to work seamlessly with 3nm or 5nm IO chiplets. Alchip's 2nm test chip achieved first-pass silicon success, reinforcing the company's high-performance ASIC leadership. The chip successfully integrated Alchip's AP-Link-3D I/O IP, demonstrating its readiness for 3D SoIC-X chiplet applications. The results also lay a foundation for the company's migration to TSMC's A16™? process node.
お知らせ • May 30Alchip Technologies, Limited Approves the Election of DirectorsAlchip Technologies, Limited at its AGM held on May 29, 2025, approved the election of Directors: Herbert Chang and Independent Directors: Andrew Kuo, Jerry Tzou, Derek C.Y. Tien and Saria Tseng.
お知らせ • Apr 21Alchip Technologies Announces Appointment of Freddy Engineer as Chief Business Officer of Alchip North AmericaAlchip Technologies announced the appointment of Mr. Freddy Engineer as Chief Business Officer (CBO) and General Manager of Alchip North America. In this role, Mr. Engineer will lead the company’s global business growth strategy while accelerating expansion of the U.S. market. Mr. Engineer will oversee worldwide sales and lead the North America Business Unit. His mandate includes expanding customer relationships, strengthening go-to-market execution, and aligning global teams to support the growing demand for the company’s high-performance custom ASIC solutions. Mr. Engineer brings more than two decades of leadership experience across the data center, communications, and cloud infrastructure markets. Most recently, he served as GM of the Semi-Custom Silicon Business at NVIDIA, where he led global business development initiatives for cloud service providers, hyperscalers, and communications customers. Prior to NVIDIA, he spent approximately 25 years at Xilinx Inc. holding several senior leadership positions, including Corporate Vice President and General Manager of the Data Center Business. During his tenure, Mr. Engineer built and scaled Xilinx’s data center organization, strengthening strategic partnerships with Tier-1 hyperscalers and other key customers. Mr. Engineer’s background in global sales, strategic accounts, and field applications engineering positions him to bridge technology strategy with customer needs as demand for Alchip’s ASIC from AI and data center enterprises continues to scale.
お知らせ • Apr 17Alchip Technologies Announces 3Dic Platform for Next-Generation Ai ProcessorsAlchip Technologies said its 3DIC platform is driving more efficient development of next-generation AI and high-performance computing devices through flexible chiplet architectures and advanced packaging integration. AI infrastructure is in a new phase of system-level complexity. Scaling performance depends on more than transistor density. It comes down to how efficiently multiple compute dies, memory stacks, and interconnect fabrics operate as a single system. Designers are balancing performance, bandwidth, power, thermals, and manufacturability—simultaneously. Next-generation AI accelerators demand multi-terabyte-per-second memory bandwidth. Data movement consumes a growing share of total system power. Large monolithic dies face reticle limits, lower yields, and rising mask costs. Even traditional 2.5D approaches introduce interposer complexity, package size constraints, and limited flexibility for vertical integration. Alchip’s 3.5D ASIC platform addresses these challenges with a system-level approach to heterogeneous integration. It partitions large SoCs into optimized chiplets across multiple process nodes. Compute dies scale on leading-edge technologies, while I/O and memory functions remain on cost-efficient nodes to improve yield, reduces cost, and accelerates deployment. The platform combines horizontal chiplet scaling with selective vertical die stacking. This hybrid 3.5D architecture delivers higher interconnect density and significantly greater design flexibility than conventional approaches. Alchip integrates this architecture with advanced packaging technologies including CoWoS-S, CoWoS-R, CoWoS-L, and TSMC-SoIC-X. The result is high-bandwidth, low-latency die-to-die connectivity that supports multi-terabyte-per-second aggregate throughput. The platform is currently delivering up to 3–5x higher interconnect density using 30-40% less energy per bit at a lower latency of up to 35%. The platform co-designs die placement, heat dissipation, and power delivery to improve efficiency. Shorter vertical power paths and optimized power delivery networks enhance performance. Integrated thermal strategies support advanced data center cooling approaches. The 3DIC platform also provides a unified design and integration flow across silicon, packaging, and system layers. This reduces development friction and allows designers to focus on workload optimization rather than infrastructure integration. Alchip’s 3DIC platform is ideal for hyperscale cloud providers, AI accelerator startups, and HPC system companies developing custom silicon. A typical configuration may include multiple compute chiplets on advanced nodes, I/O dies on mature nodes, and HBM stacks within a single package. Systems are now reaching multi-kilowatts powers levels. The ASIC platform extends the company’s long-standing leadership in advanced-node ASIC design and 2.5D/3DIC integration.
お知らせ • Mar 09Alchip Technologies, Limited, Annual General Meeting, May 26, 2026Alchip Technologies, Limited, Annual General Meeting, May 26, 2026. Location: 3 floor no,168, ching yeh 4th rd., jhongshan district, taipei city Taiwan
お知らせ • Sep 04Alchip 3DIC Test Chip Tape Out Validates Ecosystem ReadinessAlchip Technologies validated its 3DIC ecosystem readiness with results from its 3DIC test chip tape out. The results vaulted Alchip into a clear 3DIC technology leadership because it validated an entire, integrated 3DIC solution, as well as its various elements. The test chip provided CPU/NPU core demonstration, UCIe and PCIe PHY preparation, Lite-IO infrastructure, and third-party IP. The latter is particularly important because any 3DIC proven IP is hard to find. Alchip's 3DIC test chip success holds greater than normal implications because it provided technical validation of the company's 3DIC ecosystem. Alchip's growing ASIC ecosystem assures AI and HPC developers of a fast time-to-design, accurate pathway for highly complex ASIC devices. Alchip's ecosystem encompasses a technology-specific design flow, package design flow, die-to-die IP, and interconnect. Tape out validation is a critical step because 3DIC elements differ significantly from their 2D counterparts. Alchip's device integrates a 3nm top die and a 5nm base die, assembled using TSMC's SoIC®?-X packaging technology. It is designed to stress test power density and thermal dissipation challenges inherent in 3D integration. The results also inform future 3DIC designs incorporating 2nm and 3nm stacked chiplets. The chip includes a CPU, NPU core and high-power logic on the top die. The base die integrates a network-on-chip, L3 cache, and interface IP. The two dies are connected using APLink-3D Lite IO. The tape out validated several critical 3DIC capabilities, including: Cross-die synchronous die-to-die IP. Design-for-test strategies with redundancy, repair, and process monitoring. Signal and power integrity analysis for 3D stacking. Thermal and mechanical simulations for vertical integration. 3D physical design implementation and verification. The dual-die design required a new approach to physical and logical integration. The EDA tools and design methods were updated to support co-design across both dies. Sign-off included electrical, timing, and mechanical integrity across the full 3D assembly. The company tested Interface IP, architected specifically for 3DIC. Interoperability and full functionality requested new IP. Each die, especially the bottom die, requires custom PHY implementations for protocols such as UCIe, and PCIe. 3DI/O timing represents another major advancement. Alchip has limited die-to-die latency to 40 picoseconds, enabling timing paths that span dies without degrading performance. A fully integrated 3D clocking structure ensure coherent operation across both layers with minimal timing skew. Four IP vendors participated in the test chip program. Two contributed proven hard macros. Two others evaluated new IP on the test platform. An EDA flow vendor collaborated to ensure tool and methodology readiness.
お知らせ • Jul 22Alchip Technologies, Limited Introduces 2nm Design PlatformAlchip Technologies, Limited has received the first wafers from its 2nm Design Platform and is actively engaged with customers on high performance 2nm ASIC development. The new 2nm Design Platform facilitates the physical design of a 2nm chip using multiple types of 2.5D/3D technologies. It supports the development of 5nm or 3nm IO chiplets that work in conjunction with 2nm compute dies. The complete physical design methodology supports technology up to 2nm, and advanced packaging including CoWoS®?-S/R/L 2.5D/3D/3D package, System on Integrated Chips (TSMC-SoIC®?-X), die-to-die IP, and IO chiplet design. System on Wafer (TSMC-SoW™?) 3DIC solutions are on track to be supported as well. The 2nm process node introduces a complex layout structure, with a significantly greater variety of standard cells that make placement and signal/power routing more challenging. Alchip's design methodology reduces turnaround time in both design implementation and verification by proactively addressing all side effects before floor planning and clock/power planning stages. From a packaging standpoint, power density and thermal dissipation per mm2 at the 2nm node are higher because of a larger gate count and faster operating speed. While 2nm IO chiplets are not yet available, Alchip's 2nm Design Platform provides the more practical approach, enabling 2nm compute dies to work seamlessly with 3nm or 5nm IO chiplets. Alchip's 2nm test chip achieved first-pass silicon success, reinforcing the company's high-performance ASIC leadership. The chip successfully integrated Alchip's AP-Link-3D I/O IP, demonstrating its readiness for 3D SoIC-X chiplet applications. The results also lay a foundation for the company's migration to TSMC's A16™? process node.
お知らせ • May 30Alchip Technologies, Limited Approves the Election of DirectorsAlchip Technologies, Limited at its AGM held on May 29, 2025, approved the election of Directors: Herbert Chang and Independent Directors: Andrew Kuo, Jerry Tzou, Derek C.Y. Tien and Saria Tseng.
お知らせ • May 01Alchip Technologies, Limited to Report Q1, 2025 Results on May 09, 2025Alchip Technologies, Limited announced that they will report Q1, 2025 results on May 09, 2025
お知らせ • Mar 03Alchip Technologies, Limited, Annual General Meeting, May 29, 2025Alchip Technologies, Limited, Annual General Meeting, May 29, 2025. Location: 3 floor no,168, ching yeh 4th rd., jhongshan district, taipei city Taiwan
お知らせ • Mar 01Alchip Technologies, Limited Proposes Dividend Distribution for the Period from January 1, 2024 to December 31, 2024The Board of Directors of Alchip Technologies, Limited Proposed Dividend Distribution for the period from January 1, 2024 to December 31, 2024. Appropriations of earnings in cash dividends to shareholders TWD 40.05 per share. Total amount of cash distributed to shareholders TWD 3,232,587,572.
お知らせ • Feb 20Alchip Technologies, Limited to Report Q4, 2024 Results on Feb 27, 2025Alchip Technologies, Limited announced that they will report Q4, 2024 results on Feb 27, 2025
お知らせ • Nov 06Alchip Reveals 2Nm Test Chip PlanAlchip Technologies reported that it has taped out a 2nm test chip and expects the results by the first quarter of next year. It also announced that it is actively engaged with customers on high performance 2nm ASIC development. The two revelations put Alchip among the first wave of IC innovators to successfully adopted the revolutionary gate all-around transistor architecture. The test chip features high-speed SRAM and automatic place-and-route design to ensure optimal performance. It also includes silicon performance monitors for real-time insights and integrates Alchip's Lite I/O with shared and non-shared power domains, positioning it to handle 3DIC options. The test chip will establish the design flow and methodology for the latest gate all-around and nanosheet transistor structures. It will also generate power, performance, and area data from the 2nm process technology. Alchip taped out its test chip in September and sees it as a critical step in maintaining its high-performance ASIC advanced technology leadership, because the results will help the company prepare for its future migration to the A16 manufacturing. Although it's a monolithic design, the Alchip's 2nm test chip integrates and validates the company's AP-Link-3D I/O IP for potential use in future 3D-SoIC-X chiplets.
お知らせ • Nov 02Alchip Technologies, Limited Announces the Establishment of the First Nomination CommitteeAlchip Technologies, Limited announced the establishment of the first Nomination Committee of the company. Name of the new position holder: Johnny Shyang-Lin Shen, The CEO of the Company. Mao-Wei Hung, Professor, Department of International Business, National Taiwan University. Brian Chiang, Managing Director of Walden International Taiwan Co. Ltd. Effective date of the new member: November 1, 2024. The committee convener is Mr. Mao-Wei Hung.
お知らせ • Oct 25Alchip Technologies, Limited to Report Q3, 2024 Results on Nov 01, 2024Alchip Technologies, Limited announced that they will report Q3, 2024 results on Nov 01, 2024
お知らせ • Oct 17Alchip Technologies, Limited Reveals 3DIC Design Optimization KeysAlchip Technologies, Limited has revealed that it has optimized 3DIC designs by overcoming four critical challenges. The announcement came through a technical presentation at the 2024 TSMC Open Innovation Platform (OIP) Ecosystem Forum. The paper, "Efficient 3D Chiplet Stacking Using TSMC-SoIC," describes how Alchip used a third-party EDA tool to overcome four complex technical challenges. In the paper, Erez Shaizaf, Alchip's Chief Technical Officer, identifies three major barriers to 3DIC success: power delivery, dies electrical interconnect, and system-wide thermal challenges. He points out that power delivery really encompasses three separate challenges: power integrity, power grid design (including through silicon via distribution), and power integrity simulation and sign-off. Dies electrical interconnect are identified as low clock skew across dies, process variation immunity, noise immunity, data transmission across different power domains, inter-die setup/hold timing margin, PPA optimized IO cells for clock and data, and redundancy strategy. The paper details thermal challenges as 3DIC thermal characterization covering increased power density, 3D non-uniform power mapping, 3D thermal crosstalk effects, package, and system cooling solution modeling.
お知らせ • Aug 24Alchip Technologies, Limited Announces Cash Dividend, Payable on October 16, 2024Alchip Technologies, Limited announced cash dividend of Common share is USD 56,300,842. The Chairman was authorized by the Board to adjust the dividend payout ratio. The actual dividend should be subject to the exchange rate of conversion upon the receipt of the dividend by the Company’s stock agent. The cash dividend will round down to the nearest Taiwan Dollar. The total amount of round down from the shareholders will be counted as the other income of the Company. Ex-rights (ex-dividend) trading date: September 12, 2024. Ex-rights (ex-dividend) record date: September 20, 2024. Payment date of common stock cash dividend distribution: October 16, 2024.
お知らせ • Aug 16Alchip Technologies, Limited to Report Q2, 2024 Results on Aug 23, 2024Alchip Technologies, Limited announced that they will report Q2, 2024 results on Aug 23, 2024
お知らせ • May 16Alchip Technologies, Limited announced that it expects to receive funding from Amazon.com, Inc.Alchip Technologies, Limited announced a private placement that it will issue 224,537 common shares to receive funding on May 14, 2024. The transaction will include participation from new investor, Amazon.com, Inc. The transaction has been approved by the board of directors of the company.
お知らせ • Apr 28Alchip Technologies, Limited to Report Q1, 2024 Results on May 03, 2024Alchip Technologies, Limited announced that they will report Q1, 2024 results on May 03, 2024
お知らせ • Apr 12Alchip Technologies Showcases High-Performance Computing Successes at CDNLiveAlchip Technologies Ltd. will exhibit at Cadence CDNLive on April 17th 2024. The company will demonstrate its advanced technology, advanced packaging, and chiplet design capabilities. At its booth, Alchip will demonstrate ASIC-industry leading high-performance computing design and artificial intelligence expertise, which accounts for 85% of its revenue. Alchip 5nm designs is in mass production and the company is currently enabling 4nm and 3nm designs, while actively readying their 2nm capabilities. Alchip will also discuss its successfully produced CoWoS®? device with 3nm and high-bandwidth memory capabilities. The company has successfully completed complex CoWoS-S and CoWos-R designs in multiple ongoing programs, with proven mass production of advanced CoWoS and MCM packages. Across the board, Alchip has developed an enviable track record of right-the-first-time, success. It has gone to mass production on a high power chiplet design that operates at 800W and features a 3x reticle interposer. Alchip has also executed a full reticle size design (>800mm2) at leading edge FinFET nodes, and one of the CoWoS packages (70x80mm2) in production.
お知らせ • Mar 02+ 1 more updateAlchip Technologies, Limited, Annual General Meeting, May 30, 2024Alchip Technologies, Limited, Annual General Meeting, May 30, 2024. Location: 3F,No.168,Jingye 4th Rd. Zhongshan Dist., (Grand Victoria Hotel) Taipei City Taiwan Agenda: To consider The Business Report of 2023; Audit committee's Review Report on 2023 Consolidated Financial Statements; The Distribution of Bonus to Employees and Directors of the Company; 2023 Private Placement of Common Shares Processing Status Report; and to discuss other matters.
お知らせ • Jan 18Alchip Technologies, Limited has filed a Follow-on Equity Offering in the amount of TWD 12.95 billion.Alchip Technologies, Limited has filed a Follow-on Equity Offering in the amount of TWD 12.95 billion. Security Name: Global Depositary Receipts Security Type: Depositary Receipt (Common Stock) Securities Offered: 3,700,000 Price\Range: TWD 3500
お知らせ • Dec 14Alchip Unveils AI 3Dic Design and IP PlatformAlchip Technologies revealed that the company presented a paper at the TSMC 2023 Taiwan Open Innovation Platform®?Ecosystem Forum showcasing its ground-breaking collaborative advanced artificial intelligence (AI) 3DIC chiplet design and integrated IP methodology. Their revolutionary platform focuses on dramatically increasing the computational power required to handle complex neural networks and large datasets. Traditional architectures struggle to efficiently meet these requirements. But now, advanced SerDes IP technology enables larger scale with 2.5D and 3D package interconnection that consumes less power, occupies a smaller footprint, and operates with greater efficiency. 3DIC integration stores larger, more complex neural networks directly on one chiplet, reducing frequent data transfers to external memory, according to the paper. This enhances computational efficiency, reduces energy consumption, and enables real-time processing of larger datasets. The 3DIC technology stacks compute dies on top of memory and interconnect dies using high-density through-silicon-vias (TSV) and hyper bumps to increase compute transistor density, larger SRAM die, shorter interconnects, improved power efficiency with minimal latency, the authors said. The paper envisions combining IP-driven interconnects with 3DIC chiplets to address daunting challenges computational power, memory capacity, and interconnect optimization challenges. AI chip designers are now freed to push the boundaries of AI capabilities, leading to more powerful, efficient, and scalable artificial intelligence systems. Alchip revealed in the presentation that they designed the 3DIC device using TSMC's CoWoS®? advanced packaging to integrate the advanced SerDes IP. The package design has undergone thorough simulation for signal integrity (SI), power integrity (PI), and thermal considerations. A third-party user provided guidance on package breakout, thermal management, and PI consideration and have successfully completed a comprehensive system design, the paper announced.
お知らせ • Nov 23Alchip Unveils First Automotive ASIC Design PlatformAlchip Technologies, Limited rolled out the semiconductor industry’s first Automotive ASIC platform at the Design Solutions Forum 2023. The platform targets the specialized needs of the global automotive industry. The Automotive platform streamlines the ASIC design needs of global automotive IC module and component manufacturers, as well as automotive companies themselves. Alchip saw significant pre-announcement interest from companies across Europe, Japan, the United States and Asia. The platform consists of six modules: Design for Autonomous Driving (AD)/Advanced Driver Assistance System (ADAS), Design for Safety, Design for Test, Design for Reliability, Automotive Chip Sign-off, and Automotive Chip Manufacturing (MFG) Service. Design for AD/ADAS is the platform’s starting point. Its Ultra-scale design capabilities integrates Central Processing Unit (CPU) and Neural Processing Unit (NPU) into the smallest possible die size, while meeting aggressive higher performance and lower power consumption required by automotive applications. The Design for Safety module follows the ISO26262 pre-scribed flow that includes required isolated TMR/Lock-Step design methodology. The module also features an experienced safety manager and includes the mandated Development Interface Agreement (DIA) that defines the relationship between the manufacturer and the supplier throughout the entire automotive safety lifecycle and activities. Design for Reliability includes enhanced Electromigration (EM) as part of silicon lifecycle management. It also covers AEC-Q grade IP sourcing and implementation. The Automotive Chip Manufacturing Service works with IATF16949 approved manufacturing suppliers. Services include tri-temp testing by target AEC-Q grade, automotive wafer, automotive substrate, assembly and burn-in. Design for Test capabilities support In System Test (IST) and MBIST/LBIST design, critical and redundancy logic for yield harvest, automotive-level ATPG coverage, and physical-aware ATPG. The final sign-off module covers an aging library based on a customer mission profile, OD/UD/AVS/DVFS library support, and the final Design for Manufacturing sign-off.
お知らせ • Aug 23Alchip Technologies, Limited Announces Cash Dividend for 2023Alchip Technologies, Limited announced cash dividend per share of Common share is TWD 12.92 for 2023. The cash dividend of Common share is USD 30,268,787. The dividend per share is based on the total number of outstanding shares which are 74,077,185 as of August 18, 2023 and the foreign exchange rate which is based on the spot rate(TWD 31.97) set by the Bank of Taiwan on August 21, 2023. The cash dividend per share is TWD 13.06330849. The actual dividend should be subject to the exchange rate of conversion upon the receipt of the dividend by the Company's stock agent.
お知らせ • Jun 27Alchip Technologies, Limited announced that it expects to receive TWD 999.12 million in funding from Wistron CorporationAlchip Technologies, Limited announced a private placement of 690,000 shares at an issue price of TWD 1,448 per share for proceeds of TWD 999,120,000 on June 26, 2023. The transaction will include participation from new investor Wistron Corporation.
お知らせ • Feb 02Alchip Technologies Announces 3DFabric Alliance Support PlansAlchip Technologies is putting teeth into its role as a founding member of TSMC’s 3DFabric Alliance by enhancing its 3nm process technology and advanced packaging capabilities. The company supports the foundry initiative, announced in late October, seeing it as a market driver that will deliver Alchip’s most advanced high-performance computing ASIC technology to leading edge customer applications. TSMC’s 3DFabric is a comprehensive family of 3D silicon stacking and advanced packaging technologies that unleash customer’s innovation in system level approach. It consists of TSMC’s frontend technologies or TSMC-SoIC (System on Integrated Chips), dedicated fabs for 3D stacked dies’ assembling and testing, and TSMC 3DFabric’s backend technologies include CoWoS and InFO family of packaging technologies. The TSMC 3DFabric Alliance is the latest addition to TSMC’s Open Innovation Platform (OIP). The new alliance partners have early access to TSMC’s 3DFabric technologies, enabling them to develop and optimize their solutions in parallel with TSMC. This gives customers early availability to EDA, IP, memory, outsourced semiconductor assembly and test (OSAT), substrate, and testing. Alchip has been taking 3nm customer ASIC designs and tapeout its first test chip in January 2023. It became the first dedicated high-performance ASIC company to announce total design and production ecosystem readiness targeting TSMC’s latest N3E process technology. On the advanced packaging front, Alchip is fine tuning its industry leading chip-on-safer-on-substrate (CoWoS) packaging capability. CoWoS improves overall chip interconnect density and performance and is critical to nearly every high-performance computing (HPC) ASIC. CoWoS is a 2.5D wafer-level multi-chip packaging technology that incorporates side-by-side die on a silicon interposer. Micro-bumps bond individual chips to a silicon interposer, forming a chip-on-wafer. Packaging is completed by bonding to a package substrate. CoWoS chiplet sets include a high-performance system-on-a-chip (SoC) and a high-performance memory (HBM3 or HBM2E) block. Alchip’s CoWoS service covers all CoWoS package types such as CoWoS-S, CoWoS-R and CoWoS-L.
お知らせ • Nov 05Alchip Technologies, Limited Announces Appointment of Daniel Wang as Corporate Governance Officer, with Effect from November 4, 2022Alchip Technologies, Limited announced appointment of Daniel Wang as Corporate Governance Officer, with effect from November 4, 2022. Daniel Wang is the CFO of the company.
お知らせ • Nov 04Alchip Technologies, Limited to Report Q3, 2022 Results on Nov 04, 2022Alchip Technologies, Limited announced that they will report Q3, 2022 results at 2:30 PM, Taipei Standard Time on Nov 04, 2022
お知らせ • Aug 27Alchip Technologies, Limited Announces Cash DividendThe board of Alchip Technologies, Limited the cash dividend of Common share is USD 26,772,486. The Chairman was authorized by the Board to adjust the dividend payout ratio. The actual dividend should be subject to the exchange rate of conversion upon the receipt of the dividend by the Company¡y's stock agent. Ex-rights (ex-dividend) trading date is September 18, 2022. Ex-rights (ex-dividend) record date is September 24, 2022.
お知らせ • Jun 22Alchip Technologies, Limited Announces Change of Accounting OfficerAlchip Technologies, Limited appointed Yuki Jin, Financial Controller of China region as Accounting officer in place of Nancy Chan, Financial Controller. Effective date: June 20, 2022.
お知らせ • Jun 16Alchip Technologies Offers 3nm ASIC Design ServicesAlchip Technologies announced that its high-performance computing ASIC services are now taking 3nm designs and targeting its first test chip for first quarter 2023. The company will unveil its chiplet technology at the TSMC North America Technology Symposium on June 16. Alchip becomes the first dedicated high-performance ASIC company to announce total design readiness of their design and production ecosystem. The new service targets TSMC’s latest N3E process technology. The company revealed that it completed its design technology and infrastructure during the current quarter and will make available its design methodology within a couple of weeks. Other assets in place include a complete library of best-in-class 3rd party IP covering DDR5, GDDR6, HBM2E, HBM3, PCIe5, and 112G SERDES IP from Tier 1 providers. 4nm Test Chip Tape-out Next Quarter: Alchip also revealed that its first 4nm test chip, targeting TSMC’s N4P process technology will be taped out early in August. Design methodology, design technology and infrastructure and test chips specification had all been finalized at the end of last year. APLink 4.0 supports N5/N4P die-to-die connection for advanced packaging designs. Alchip is traded on the Taiwan Stock Exchange, with Global Repository Receipts trading on the Luxembourg Exchange.
お知らせ • Jun 11Alchip Technologies, Limited Approves the Appointment of Herbert Chang as DirectorAlchip Technologies, Limited at its AGM held on June 10, 2022, approved the appointment of Herbert Chang as Director.
お知らせ • May 12Alchip Technologies, Limited Reaffirms Revenue Guidance for the Year 2022Alchip Technologies, Limited reaffirmed revenue guidance for the year 2022. The company left unchanged its forecast for another promising revenue growth in 2022.
お知らせ • Mar 07+ 1 more updateAlchip Technologies, Limited Announces Personnel Change of GM of US Business UnitAlchip Technologies, Limited announced personnel change of GM of US Business Unit. Name, title, and resume of the previous position holder: Hiroyuki Nagashima and Name, title, and resume of the new position holder: Yaw-Lin Hwang, Effective date is March 4, 2022.
お知らせ • Mar 06+ 1 more updateAlchip Technologies, Limited Proposes Cash Dividends for the Year Ended December 31, 2021Alchip Technologies, Limited proposed cash dividends to shareholders of TWD 10.59 per share for the year ended December 31, 2021. Total amount of cash distributed to shareholders of TWD 751,235,956.
お知らせ • Mar 06Alchip Technologies, Limited, Annual General Meeting, Jun 11, 2021Alchip Technologies, Limited, Annual General Meeting, Jun 11, 2021. Location: 3F,No.168,Jingye 4th Rd. Zhongshan Dist Grand Victoria Hotel Taipei County Taiwan Agenda: To consider the business report of 2020; to consider audit committee's Review Report on 2020 Consolidated Financial Statements; to consider the distribution of Bonus to Employees and Directors of the Company; to consider amendments to the Memorandum and Articles of Association of the Company; to consider amendments to the Rules of Procedure for Shareholders Meetings of the Company; and to consider other matters.
お知らせ • Feb 05Alchip Technologies, Limited Unveils Two Sign-Off Verification Options to Accommodate Both Design Economics and Enhanced Yield ObjectivesAlchip Technologies, Limited revealed that demand for post-GDSII backend services has increased exponentially across all high-performance computing ASIC applications. The company is meeting this uptick with invested emphasis on production, packaging and test and assembly services. As a result, Alchip's post-GDSII services are experiencing high demand as systems and OEM companies face both technology challenges and engineering talent limitations associated with traditional backend services. Sophisticated high-performance frontend design resources are expensive and, depending on geographic location, somewhat scarce. The result is an uptick in companies outsourcing production, packaging, test and assembly responsibilities to ASIC companies who are far more experienced in these strategic areas. Alchip has elevated its packaging capabilities to include Chip-on-Wafer-on-Substrate (CoWoS®) first developed by TSMC and this spring is expected to announced a true 2.5D INFO capability. Alchip's CoWoS process runs on dedicated tooling and demonstrates IP performance equivalent to that of an original design. The process also includes online debugging and active thermal control. The company's in-house design substrate design capabilities assure compliance with all system requirements and establishes the frame work for critical foundry-to-final test flow. The company has also unveiled a two sign-off verification options to accommodate both design economics and enhanced yield objectives. Standard sign-off verification includes DRC/LVS/ERC checks that guard against fatal manufacturing error. A second design options calls for additional focus on Electrical, DFT, STA and/or clock verification, depending on specific customer requirements.
