お知らせ • Apr 08
Applied Materials Introduces Deposition Systems for Angstrom-Era Logic Chips
Applied Materials, Inc. introduced two chipmaking systems designed to create the smallest features in the world’s most advanced logic chips. By controlling materials deposition with atomic-level precision, the technologies enable chipmakers to build faster and more power-efficient transistors at the scale required to sustain the pace of global AI infrastructure buildout. Driven by surging demand for AI compute, the semiconductor industry is pushing the limits of scaling to squeeze more energy-efficient performance from each of the hundreds of billions of transistors in a processor chip. To address this challenge, logic chipmakers are introducing new Gate-All-Around (GAA) transistors at 2nm and beyond. The GAA transition enables much higher performance at the same power, but achieving these gains comes with dramatically higher process complexity. Building the complicated 3D structures inside a GAA transistor takes more than 500 process steps, many of which require entirely new ways of depositing materials with precision, repeatability and control – all within tolerances approaching the size of individual atoms. Applied unveiled two chipmaking systems that leverage material innovations to create some of the most complex features associated with GAA transistors. The new technologies enable deposition of metals and insulating dielectrics – essential materials that dramatically impact the performance and power efficiency of advanced chips. Precision Selective Nitride PECVD System Preserves Integrity of Shallow Trench Isolation. Next-generation AI GPUs now in development are expected to pack more than 300 billion transistors into a space the size of a postage stamp. Without proper isolation, electrons can easily diffuse into neighboring transistors, leading to parasitic capacitance, an unintended electrical drag between transistors that slows signals, wastes power and negatively impacts a chip’s performance-per-watt. In advanced transistor architectures, shallow trench isolation (STI) is used to electrically separate neighboring transistors. With this technique, a trench is etched into the surface between transistors and then filled with an insulating dielectric material such as silicon oxide, which keeps electrical charge confined and prevents unwanted leakage. These narrow isolation trenches are some of the smallest structures in a GAA device, making it difficult to maintain isolation quality during high-volume manufacturing. Once these trenches are formed, the chip goes through many additional processing steps, and over time those steps can gradually wear down the silicon oxide isolation material, negatively impacting overall chip performance. The Applied Producer Precision Selective Nitride PECVD system uses an industry-first selective bottom-up deposition process to place silicon nitride only where it’s needed in the trench. It deposits a dense silicon nitride layer on top of the silicon oxide, which helps the isolation withstand later processing steps that would otherwise recess the STI material. The process operates at low temperatures to avoid any damage to the underlayer film or structure. By preserving the original shape and height of the isolation trench, Precision Selective Nitride helps maintain consistent electrical behavior, reducing parasitic capacitance, lowering leakage, and boosting overall device performance. The Precision Selective Nitride PECVD system is now being adopted by logic chipmakers at 2nm and below GAA process nodes. Trillium ALD System Builds Complex Metal Gate Structures with Atomic-Scale Uniformity. Each GAA transistor is a switch controlled by a gate stack composed of multiple layers of metal that determine the threshold voltage needed to turn the transistor on and off. To meet the unique needs of different AI workloads, from the data center to the edge, chipmakers provide designers with a range of transistor options, with some tuned to switch faster for peak performance and others tuned to switch using the lowest amount of power. Meeting these trade-offs comes down to metal gate stack optimization based on high-precision metal deposition. In GAA transistors, the gate stack needs to completely surround multiple horizontal nanosheets spaced only around 10 nanometers apart – equivalent to around 1/10,000 the width of a human hair. Any gaps or non-uniformities in the gate stack can cause variability in the transistor’s switching characteristics and negatively impact chip performance, power consumption, reliability and yield. Conventional metal deposition approaches struggle to meet these extreme requirements. The Applied Endura Trillium ALD system is an Integrated Materials Solution designed to precisely deposit metals in the most complex GAA transistor gate stacks. The system harnesses Applied’s legacy of leadership in metal ALD technology for advanced transistor applications. By integrating multiple metal deposition steps in a single platform, Trillium gives chipmakers the flexibility to tune threshold voltage across different transistors. Trillium leverages the proven Endura platform to create and maintain an extraordinarily high vacuum. This vacuum keeps wafers protected from impurities in the cleanroom atmosphere, which is critical when depositing multiple materials in the miniscule space between silicon nanosheets. By providing angstrom-level thickness control of metal gate stack layers, Trillium ALD delivers the tunability and reliability advanced GAA transistors demand, while improving transistor performance, power and reliability. Applied’s Trillium ALD system has been an established benchmark for metal gate stack deposition at multiple generations of FinFET process nodes. The system has been highly tailored for GAA applications with new features to enable thinner work function metals and volume-less dipole materials that address the limited space in GAA structures, and it is now being adopted by logic chipmakers at 2nm and below GAA process nodes.