Astera Labs（ALABD）株式概要Astera Labs, Inc.は、クラウドおよびAIインフラ向けの半導体ベースの接続ソリューションを設計、製造、販売している。 詳細ALABD ファンダメンタル分析スノーフレーク・スコア評価0/6将来の成長5/6過去の実績2/6財務の健全性6/6配当金0/6報酬収益は年間27.33%増加すると予測されています 今年は黒字化を達成 リスク分析株式の流動性は非常に低い すべてのリスクチェックを見るALABD Community Fair Values Create NarrativeSee what others think this stock is worth. Follow their fair value or set your own to get alerts.Your Fair ValueUS$Current PriceUS$2.9198.9% 割安 内在価値ディスカウントGrowth estimate overAnnual revenue growth rate5 Yearstime period%/yrDecreaseIncreasePastFuture-83m3b2016201920222025202620282031Revenue US$2.6bEarnings US$665.8mAdvancedSet Fair ValueView all narrativesAstera Labs, Inc. 競合他社Credo Technology Group HoldingSymbol: NasdaqGS:CRDOMarket cap: US$36.6bShenzhen Techwinsemi TechnologySymbol: SZSE:001309Market cap: CN¥135.6bBIWIN Storage TechnologySymbol: SHSE:688525Market cap: CN¥136.8bMontage TechnologySymbol: SHSE:688008Market cap: CN¥263.1b価格と性能株価の高値、安値、推移の概要Astera Labs過去の株価現在の株価US$2.9152週高値US$3.0552週安値US$2.87ベータ3.361ヶ月の変化0%3ヶ月変化14.71%1年変化n/a3年間の変化n/a5年間の変化n/aIPOからの変化14.71%最新ニュースお知らせ • 1hAstera Labs, Inc. Provides Earnings Guidance for the Second Quarter ending June 30, 2026Astera Labs, Inc. provided earnings guidance for the second quarter ending June 30, 2026. For the quarter, the company expects Revenue within a range of $355 million to $365 million, GAAP diluted earnings per share of approximately $0.44 to $0.46 on weighted-average diluted shares outstanding of approximately 184 million.お知らせ • May 07Astera Labs Announces Scorpio X-Series 320 Lane Smart Fabric SwitchAstera Labs, Inc. announced the Scorpio X-Series 320 Lane Smart Fabric Switch, the industry's largest open, memory-semantic fabric switch engineered to improve token economics and support large scale-up clusters with minimal latency. Astera Labs also announced an expanded Scorpio P-Series PCIe fabric switch family—now spanning 32 to 320 lane configurations—designed to give data center architects at AI labs, hyperscalers, and neo-clouds the flexibility to rapidly scale compute capacity across diverse accelerators for training and serving frontier AI models. Scorpio's software-defined architecture is designed to integrate seamlessly with leading merchant and custom silicon, enabling AI labs and hyperscalers to integrate and deploy new accelerator platforms for both training and inference. Its memory-semantic connectivity enables accelerators to access fabric resources through native load/store operations, eliminating software overhead and improving fabric efficiency at scale. Scorpio X-Series delivers simplified high-radix scale-up topologies, cutting hops and reducing end-to-end latency across the cluster. Newly introduced Hypercast and In-Network Compute engines accelerate collective operations by up to 2x to maximize GPU utilization and tokens-per-watt performance. Rounding out the family, the Scorpio P-Series complements the X-Series in front-end network and AI compute system deployments, to deliver resiliency, dynamic configurability, and broad interoperability. COSMOS software unifies the platform with purpose-built resiliency and serviceability, delivering non-disruptive firmware updates, OpenBMC management, and real-time telemetry. Hypercast and In-Network Compute are configured through COSMOS, extending its capabilities to now include platform performance optimizations. These capabilities are designed to maximize uptime, accelerator utilization, and ensure operational reliability for continuous production workloads while accelerating rack validation and compressing time-to-deployment. COSMOS extends across Astera Labs' complete rack-scale portfolio of fabric switches, copper connectivity, and optical solutions, enabling composable AI infrastructure from a single unified management software stack. The Scorpio X-Series 320 Lane Smart Fabric Switch is shipping into a merchant scale-up switch silicon market projected to reach $20 billion by 2030, with production ramp in Second Half 2026. Astera Labs will showcase the Scorpio X-Series 320 Lane and its complete rack-scale connectivity portfolio at Computex 2026 (Taipei, June 2-5), including industry-first PCIe 6 scale-up optics demonstrations leveraging COSMOS for end-to-end link management.お知らせ • Apr 26Astera Labs, Inc., Annual General Meeting, Jun 04, 2026Astera Labs, Inc., Annual General Meeting, Jun 04, 2026. Location: offices of, astera labs, inc., at 2345 north first street, san jose, california 95131., san jose. United Statesお知らせ • Apr 09Ultra Accelerator Link Consortium Publishes Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G PerformanceUltra Accelerator Link Consortium, the industry standards organization developing the open scale-up interconnect for next-generation AI workloads, announced the ratification of the next UALink Specification, which encompasses three major additions – In-Network Compute, Chiplet Definition, and Manageability. The new specifications support the deployment of UALink solutions in multi-workload environments, while simultaneously helping improve UALink technology efficiency, performance for AI workloads and ease of implementation. The UALink Consortium provides a standardized foundation for accelerator connectivity at scale, helping drive innovation, increase deployment flexibility and support the rapidly growing performance demands of next-generation AI workloads. The new specification update is facilitated through UALink Consortium’s open governance model, which fosters innovation while enabling a robust, multi-vendor supply chain, providing system designers and cloud providers with the necessary flexibility to deploy interoperable solutions without vendor lock-in. New UALink Specifications: UALink Common Specification 2.0 introduces In-Network Compute for UALink technology, facilitating computation and communication between accelerators. Reduces latency, saves bandwidth, and improves scaling efficiency for distributed training and inference for AI solutions for complex and multi-workload environments for UALink systems. UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0 split the DL/PL Specification from the UALink Common Specification to enable UALink to move quickly as new physical layers and speeds are needed by the industry without requiring changes to the other specifications. UALink Manageability Specification 1.0 introduces UALink as a system with centralized control and management planes. Utilizes standardized protocols, modeling and APIs like gNMI, Yang, SAI and Redfish. UALink Chiplet Specification 1.0 defines the necessary information to integrate UALink technology into chiplet-based SoCs, including interfaces, form factors, flow control and chiplet management standardization. Fully compliant with the UCIe 3.0 Specification for simplified integration into existing chiplet ecosystems. All of the UALink specifications are available for public download.お知らせ • Apr 03Astera Labs, Inc. to Report Q1, 2026 Results on May 05, 2026Astera Labs, Inc. announced that they will report Q1, 2026 results After-Market on May 05, 2026お知らせ • Feb 11+ 1 more updateAstera Labs, Inc. Announces Chief Financial Officer Changes, Effective March 2, 2026Astera Labs, Inc. appointed Desmond Lynch, age 46, as Chief Financial Officer, effective March 2, 2026. Desmond Lynch previously served as Senior Vice President, Finance and Chief Financial Officer of Rambus Inc. from August 2022 until February 2026 and served as the Vice President of Finance and Investor Relations of Rambus from 2020 until 2022. In addition, Desmond Lynch served as Vice President, Finance of Knowles Corporation, an audio solutions company, from 2019 to 2020. Previously, Desmond Lynch served as Vice President, Finance/Senior Director, Financial Planning and Analysis at Renesas Electronics Corporation/Integrated Device Technology, Inc., an analog and mixed signal semiconductor company, from 2016 to 2019. Desmond Lynch also served as Director, Financial Planning and Analysis at Atmel Corporation, a semiconductor company, from 2010 to 2016, prior to its acquisition by Microchip Technology. Desmond Lynch received a bachelor's degree in Accounting and Finance from the University of Glasgow, Scotland, in 2000, and is a Chartered Accountant with the Institute of Chartered Accountants of Scotland. On February 4, 2026, Michael Tate notified the Company of his retirement as Chief Financial Officer of the Company, effective March 2, 2026. Mr. Tate remains an employee of the Company and will transition to a role as Strategic Advisor to the CEO until September 1, 2026.最新情報をもっと見るRecent updatesお知らせ • 1hAstera Labs, Inc. Provides Earnings Guidance for the Second Quarter ending June 30, 2026Astera Labs, Inc. provided earnings guidance for the second quarter ending June 30, 2026. For the quarter, the company expects Revenue within a range of $355 million to $365 million, GAAP diluted earnings per share of approximately $0.44 to $0.46 on weighted-average diluted shares outstanding of approximately 184 million.お知らせ • May 07Astera Labs Announces Scorpio X-Series 320 Lane Smart Fabric SwitchAstera Labs, Inc. announced the Scorpio X-Series 320 Lane Smart Fabric Switch, the industry's largest open, memory-semantic fabric switch engineered to improve token economics and support large scale-up clusters with minimal latency. Astera Labs also announced an expanded Scorpio P-Series PCIe fabric switch family—now spanning 32 to 320 lane configurations—designed to give data center architects at AI labs, hyperscalers, and neo-clouds the flexibility to rapidly scale compute capacity across diverse accelerators for training and serving frontier AI models. Scorpio's software-defined architecture is designed to integrate seamlessly with leading merchant and custom silicon, enabling AI labs and hyperscalers to integrate and deploy new accelerator platforms for both training and inference. Its memory-semantic connectivity enables accelerators to access fabric resources through native load/store operations, eliminating software overhead and improving fabric efficiency at scale. Scorpio X-Series delivers simplified high-radix scale-up topologies, cutting hops and reducing end-to-end latency across the cluster. Newly introduced Hypercast and In-Network Compute engines accelerate collective operations by up to 2x to maximize GPU utilization and tokens-per-watt performance. Rounding out the family, the Scorpio P-Series complements the X-Series in front-end network and AI compute system deployments, to deliver resiliency, dynamic configurability, and broad interoperability. COSMOS software unifies the platform with purpose-built resiliency and serviceability, delivering non-disruptive firmware updates, OpenBMC management, and real-time telemetry. Hypercast and In-Network Compute are configured through COSMOS, extending its capabilities to now include platform performance optimizations. These capabilities are designed to maximize uptime, accelerator utilization, and ensure operational reliability for continuous production workloads while accelerating rack validation and compressing time-to-deployment. COSMOS extends across Astera Labs' complete rack-scale portfolio of fabric switches, copper connectivity, and optical solutions, enabling composable AI infrastructure from a single unified management software stack. The Scorpio X-Series 320 Lane Smart Fabric Switch is shipping into a merchant scale-up switch silicon market projected to reach $20 billion by 2030, with production ramp in Second Half 2026. Astera Labs will showcase the Scorpio X-Series 320 Lane and its complete rack-scale connectivity portfolio at Computex 2026 (Taipei, June 2-5), including industry-first PCIe 6 scale-up optics demonstrations leveraging COSMOS for end-to-end link management.お知らせ • Apr 26Astera Labs, Inc., Annual General Meeting, Jun 04, 2026Astera Labs, Inc., Annual General Meeting, Jun 04, 2026. Location: offices of, astera labs, inc., at 2345 north first street, san jose, california 95131., san jose. United Statesお知らせ • Apr 09Ultra Accelerator Link Consortium Publishes Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G PerformanceUltra Accelerator Link Consortium, the industry standards organization developing the open scale-up interconnect for next-generation AI workloads, announced the ratification of the next UALink Specification, which encompasses three major additions – In-Network Compute, Chiplet Definition, and Manageability. The new specifications support the deployment of UALink solutions in multi-workload environments, while simultaneously helping improve UALink technology efficiency, performance for AI workloads and ease of implementation. The UALink Consortium provides a standardized foundation for accelerator connectivity at scale, helping drive innovation, increase deployment flexibility and support the rapidly growing performance demands of next-generation AI workloads. The new specification update is facilitated through UALink Consortium’s open governance model, which fosters innovation while enabling a robust, multi-vendor supply chain, providing system designers and cloud providers with the necessary flexibility to deploy interoperable solutions without vendor lock-in. New UALink Specifications: UALink Common Specification 2.0 introduces In-Network Compute for UALink technology, facilitating computation and communication between accelerators. Reduces latency, saves bandwidth, and improves scaling efficiency for distributed training and inference for AI solutions for complex and multi-workload environments for UALink systems. UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0 split the DL/PL Specification from the UALink Common Specification to enable UALink to move quickly as new physical layers and speeds are needed by the industry without requiring changes to the other specifications. UALink Manageability Specification 1.0 introduces UALink as a system with centralized control and management planes. Utilizes standardized protocols, modeling and APIs like gNMI, Yang, SAI and Redfish. UALink Chiplet Specification 1.0 defines the necessary information to integrate UALink technology into chiplet-based SoCs, including interfaces, form factors, flow control and chiplet management standardization. Fully compliant with the UCIe 3.0 Specification for simplified integration into existing chiplet ecosystems. All of the UALink specifications are available for public download.お知らせ • Apr 03Astera Labs, Inc. to Report Q1, 2026 Results on May 05, 2026Astera Labs, Inc. announced that they will report Q1, 2026 results After-Market on May 05, 2026お知らせ • Feb 11+ 1 more updateAstera Labs, Inc. Announces Chief Financial Officer Changes, Effective March 2, 2026Astera Labs, Inc. appointed Desmond Lynch, age 46, as Chief Financial Officer, effective March 2, 2026. Desmond Lynch previously served as Senior Vice President, Finance and Chief Financial Officer of Rambus Inc. from August 2022 until February 2026 and served as the Vice President of Finance and Investor Relations of Rambus from 2020 until 2022. In addition, Desmond Lynch served as Vice President, Finance of Knowles Corporation, an audio solutions company, from 2019 to 2020. Previously, Desmond Lynch served as Vice President, Finance/Senior Director, Financial Planning and Analysis at Renesas Electronics Corporation/Integrated Device Technology, Inc., an analog and mixed signal semiconductor company, from 2016 to 2019. Desmond Lynch also served as Director, Financial Planning and Analysis at Atmel Corporation, a semiconductor company, from 2010 to 2016, prior to its acquisition by Microchip Technology. Desmond Lynch received a bachelor's degree in Accounting and Finance from the University of Glasgow, Scotland, in 2000, and is a Chartered Accountant with the Institute of Chartered Accountants of Scotland. On February 4, 2026, Michael Tate notified the Company of his retirement as Chief Financial Officer of the Company, effective March 2, 2026. Mr. Tate remains an employee of the Company and will transition to a role as Strategic Advisor to the CEO until September 1, 2026.株主還元ALABDAR SemiconductorAR 市場7D0%0%0%1Yn/a0%0%株主還元を見る業界別リターン: ALABDがAR Semiconductor業界に対してどのようなパフォーマンスを示したかを判断するにはデータが不十分です。リターン対市場: ALABD AR市場に対してどのようなパフォーマンスを示したかを判断するにはデータが不十分です。価格変動Is ALABD's price volatile compared to industry and market?ALABD volatilityALABD Average Weekly Movementn/aSemiconductor Industry Average Movement0%Market Average Movement0%10% most volatile stocks in AR Market0%10% least volatile stocks in AR Market0%安定した株価: ALABDの株価は、 AR市場と比較して過去 3 か月間で変動しています。時間の経過による変動: 過去 1 年間のALABDのボラティリティの変化を判断するには データが不十分です。会社概要設立従業員CEO（最高経営責任者ウェブサイト2017756Jitendra Mohanwww.asteralabs.comAstera Labs, Inc.は、クラウドおよびAIインフラ向けの半導体ベースの接続ソリューションを設計、製造、販売している。半導体ベースのミックスドシグナルコネクティビティ製品で構成され、マイクロコントローラーとセンサーのマトリックスを統合したインテリジェントコネクティビティプラットフォームとCOSMOSを提供している。同社は、リンク、フリート、RAS管理機能により、クラウドスケールでの大規模フリート向けリソースの管理と最適化を可能にするコネクティビティシステム管理・最適化ソフトウェアであるCOSMOSソフトウェアスイートを提供している。また、PCIe/CXLスマートDSPリタイマーとケーブルモジュール、クラウドとAIインフラ向けのイーサネットスマートケーブルモジュール、CXLメモリ接続コントローラー、スマートファブリックスイッチを提供している。同社はハイパースケーラーやシステムOEMメーカーにサービスを提供している。Astera Labs, Inc.は2017年に法人化され、カリフォルニア州サンノゼを拠点としている。もっと見るAstera Labs, Inc. 基礎のまとめAstera Labs の収益と売上を時価総額と比較するとどうか。ALABD 基礎統計学時価総額US$36.94b収益（TTM）US$219.13m売上高(TTM)US$852.53m168.6xPER（株価収益率43.3xP/SレシオALABD は割高か？公正価値と評価分析を参照収益と収入最新の決算報告書（TTM）に基づく主な収益性統計ALABD 損益計算書（TTM）収益US$852.53m売上原価US$207.26m売上総利益US$645.26mその他の費用US$426.13m収益US$219.13m直近の収益報告Dec 31, 2025次回決算日該当なし一株当たり利益（EPS）1.28グロス・マージン75.69%純利益率25.70%有利子負債／自己資本比率0%ALABD の長期的なパフォーマンスは？過去の実績と比較を見るView Valuation企業分析と財務データの現状データ最終更新日（UTC時間）企業分析2026/05/06 14:42終値2026/02/26 00:00収益2025/12/31年間収益2025/12/31データソース企業分析に使用したデータはS&P Global Market Intelligence LLC のものです。本レポートを作成するための分析モデルでは、以下のデータを使用しています。データは正規化されているため、ソースが利用可能になるまでに時間がかかる場合があります。パッケージデータタイムフレーム米国ソース例会社財務10年損益計算書キャッシュ・フロー計算書貸借対照表SECフォーム10-KSECフォーム10-Qアナリストのコンセンサス予想+プラス3年予想財務アナリストの目標株価アナリストリサーチレポートBlue Matrix市場価格30年株価配当、分割、措置ICEマーケットデータSECフォームS-1所有権10年トップ株主インサイダー取引SECフォーム4SECフォーム13Dマネジメント10年リーダーシップ・チーム取締役会SECフォーム10-KSECフォームDEF 14A主な進展10年会社からのお知らせSECフォーム8-K* 米国証券を対象とした例であり、非米国証券については、同等の規制書式および情報源を使用。特に断りのない限り、すべての財務データは1年ごとの期間に基づいていますが、四半期ごとに更新されます。これは、TTM（Trailing Twelve Month）またはLTM（Last Twelve Month）データとして知られています。詳細はこちら。分析モデルとスノーフレーク本レポートを生成するために使用した分析モデルの詳細は当社のGithubページでご覧いただけます。また、レポートの使用方法に関するガイドやYoutubeのチュートリアルも掲載しています。シンプリー・ウォールストリート分析モデルを設計・構築した世界トップクラスのチームについてご紹介します。業界およびセクターの指標私たちの業界とセクションの指標は、Simply Wall Stによって6時間ごとに計算されます。アナリスト筋Astera Labs, Inc. 23 これらのアナリストのうち、弊社レポートのインプットとして使用した売上高または利益の予想を提出したのは、 。アナリストの投稿は一日中更新されます。29 アナリスト機関Thomas O'MalleyBarclaysKarl AckermanBNP ParibasVivek AryaBofA Global Research26 その他のアナリストを表示
お知らせ • 1hAstera Labs, Inc. Provides Earnings Guidance for the Second Quarter ending June 30, 2026Astera Labs, Inc. provided earnings guidance for the second quarter ending June 30, 2026. For the quarter, the company expects Revenue within a range of $355 million to $365 million, GAAP diluted earnings per share of approximately $0.44 to $0.46 on weighted-average diluted shares outstanding of approximately 184 million.
お知らせ • May 07Astera Labs Announces Scorpio X-Series 320 Lane Smart Fabric SwitchAstera Labs, Inc. announced the Scorpio X-Series 320 Lane Smart Fabric Switch, the industry's largest open, memory-semantic fabric switch engineered to improve token economics and support large scale-up clusters with minimal latency. Astera Labs also announced an expanded Scorpio P-Series PCIe fabric switch family—now spanning 32 to 320 lane configurations—designed to give data center architects at AI labs, hyperscalers, and neo-clouds the flexibility to rapidly scale compute capacity across diverse accelerators for training and serving frontier AI models. Scorpio's software-defined architecture is designed to integrate seamlessly with leading merchant and custom silicon, enabling AI labs and hyperscalers to integrate and deploy new accelerator platforms for both training and inference. Its memory-semantic connectivity enables accelerators to access fabric resources through native load/store operations, eliminating software overhead and improving fabric efficiency at scale. Scorpio X-Series delivers simplified high-radix scale-up topologies, cutting hops and reducing end-to-end latency across the cluster. Newly introduced Hypercast and In-Network Compute engines accelerate collective operations by up to 2x to maximize GPU utilization and tokens-per-watt performance. Rounding out the family, the Scorpio P-Series complements the X-Series in front-end network and AI compute system deployments, to deliver resiliency, dynamic configurability, and broad interoperability. COSMOS software unifies the platform with purpose-built resiliency and serviceability, delivering non-disruptive firmware updates, OpenBMC management, and real-time telemetry. Hypercast and In-Network Compute are configured through COSMOS, extending its capabilities to now include platform performance optimizations. These capabilities are designed to maximize uptime, accelerator utilization, and ensure operational reliability for continuous production workloads while accelerating rack validation and compressing time-to-deployment. COSMOS extends across Astera Labs' complete rack-scale portfolio of fabric switches, copper connectivity, and optical solutions, enabling composable AI infrastructure from a single unified management software stack. The Scorpio X-Series 320 Lane Smart Fabric Switch is shipping into a merchant scale-up switch silicon market projected to reach $20 billion by 2030, with production ramp in Second Half 2026. Astera Labs will showcase the Scorpio X-Series 320 Lane and its complete rack-scale connectivity portfolio at Computex 2026 (Taipei, June 2-5), including industry-first PCIe 6 scale-up optics demonstrations leveraging COSMOS for end-to-end link management.
お知らせ • Apr 26Astera Labs, Inc., Annual General Meeting, Jun 04, 2026Astera Labs, Inc., Annual General Meeting, Jun 04, 2026. Location: offices of, astera labs, inc., at 2345 north first street, san jose, california 95131., san jose. United States
お知らせ • Apr 09Ultra Accelerator Link Consortium Publishes Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G PerformanceUltra Accelerator Link Consortium, the industry standards organization developing the open scale-up interconnect for next-generation AI workloads, announced the ratification of the next UALink Specification, which encompasses three major additions – In-Network Compute, Chiplet Definition, and Manageability. The new specifications support the deployment of UALink solutions in multi-workload environments, while simultaneously helping improve UALink technology efficiency, performance for AI workloads and ease of implementation. The UALink Consortium provides a standardized foundation for accelerator connectivity at scale, helping drive innovation, increase deployment flexibility and support the rapidly growing performance demands of next-generation AI workloads. The new specification update is facilitated through UALink Consortium’s open governance model, which fosters innovation while enabling a robust, multi-vendor supply chain, providing system designers and cloud providers with the necessary flexibility to deploy interoperable solutions without vendor lock-in. New UALink Specifications: UALink Common Specification 2.0 introduces In-Network Compute for UALink technology, facilitating computation and communication between accelerators. Reduces latency, saves bandwidth, and improves scaling efficiency for distributed training and inference for AI solutions for complex and multi-workload environments for UALink systems. UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0 split the DL/PL Specification from the UALink Common Specification to enable UALink to move quickly as new physical layers and speeds are needed by the industry without requiring changes to the other specifications. UALink Manageability Specification 1.0 introduces UALink as a system with centralized control and management planes. Utilizes standardized protocols, modeling and APIs like gNMI, Yang, SAI and Redfish. UALink Chiplet Specification 1.0 defines the necessary information to integrate UALink technology into chiplet-based SoCs, including interfaces, form factors, flow control and chiplet management standardization. Fully compliant with the UCIe 3.0 Specification for simplified integration into existing chiplet ecosystems. All of the UALink specifications are available for public download.
お知らせ • Apr 03Astera Labs, Inc. to Report Q1, 2026 Results on May 05, 2026Astera Labs, Inc. announced that they will report Q1, 2026 results After-Market on May 05, 2026
お知らせ • Feb 11+ 1 more updateAstera Labs, Inc. Announces Chief Financial Officer Changes, Effective March 2, 2026Astera Labs, Inc. appointed Desmond Lynch, age 46, as Chief Financial Officer, effective March 2, 2026. Desmond Lynch previously served as Senior Vice President, Finance and Chief Financial Officer of Rambus Inc. from August 2022 until February 2026 and served as the Vice President of Finance and Investor Relations of Rambus from 2020 until 2022. In addition, Desmond Lynch served as Vice President, Finance of Knowles Corporation, an audio solutions company, from 2019 to 2020. Previously, Desmond Lynch served as Vice President, Finance/Senior Director, Financial Planning and Analysis at Renesas Electronics Corporation/Integrated Device Technology, Inc., an analog and mixed signal semiconductor company, from 2016 to 2019. Desmond Lynch also served as Director, Financial Planning and Analysis at Atmel Corporation, a semiconductor company, from 2010 to 2016, prior to its acquisition by Microchip Technology. Desmond Lynch received a bachelor's degree in Accounting and Finance from the University of Glasgow, Scotland, in 2000, and is a Chartered Accountant with the Institute of Chartered Accountants of Scotland. On February 4, 2026, Michael Tate notified the Company of his retirement as Chief Financial Officer of the Company, effective March 2, 2026. Mr. Tate remains an employee of the Company and will transition to a role as Strategic Advisor to the CEO until September 1, 2026.
お知らせ • 1hAstera Labs, Inc. Provides Earnings Guidance for the Second Quarter ending June 30, 2026Astera Labs, Inc. provided earnings guidance for the second quarter ending June 30, 2026. For the quarter, the company expects Revenue within a range of $355 million to $365 million, GAAP diluted earnings per share of approximately $0.44 to $0.46 on weighted-average diluted shares outstanding of approximately 184 million.
お知らせ • May 07Astera Labs Announces Scorpio X-Series 320 Lane Smart Fabric SwitchAstera Labs, Inc. announced the Scorpio X-Series 320 Lane Smart Fabric Switch, the industry's largest open, memory-semantic fabric switch engineered to improve token economics and support large scale-up clusters with minimal latency. Astera Labs also announced an expanded Scorpio P-Series PCIe fabric switch family—now spanning 32 to 320 lane configurations—designed to give data center architects at AI labs, hyperscalers, and neo-clouds the flexibility to rapidly scale compute capacity across diverse accelerators for training and serving frontier AI models. Scorpio's software-defined architecture is designed to integrate seamlessly with leading merchant and custom silicon, enabling AI labs and hyperscalers to integrate and deploy new accelerator platforms for both training and inference. Its memory-semantic connectivity enables accelerators to access fabric resources through native load/store operations, eliminating software overhead and improving fabric efficiency at scale. Scorpio X-Series delivers simplified high-radix scale-up topologies, cutting hops and reducing end-to-end latency across the cluster. Newly introduced Hypercast and In-Network Compute engines accelerate collective operations by up to 2x to maximize GPU utilization and tokens-per-watt performance. Rounding out the family, the Scorpio P-Series complements the X-Series in front-end network and AI compute system deployments, to deliver resiliency, dynamic configurability, and broad interoperability. COSMOS software unifies the platform with purpose-built resiliency and serviceability, delivering non-disruptive firmware updates, OpenBMC management, and real-time telemetry. Hypercast and In-Network Compute are configured through COSMOS, extending its capabilities to now include platform performance optimizations. These capabilities are designed to maximize uptime, accelerator utilization, and ensure operational reliability for continuous production workloads while accelerating rack validation and compressing time-to-deployment. COSMOS extends across Astera Labs' complete rack-scale portfolio of fabric switches, copper connectivity, and optical solutions, enabling composable AI infrastructure from a single unified management software stack. The Scorpio X-Series 320 Lane Smart Fabric Switch is shipping into a merchant scale-up switch silicon market projected to reach $20 billion by 2030, with production ramp in Second Half 2026. Astera Labs will showcase the Scorpio X-Series 320 Lane and its complete rack-scale connectivity portfolio at Computex 2026 (Taipei, June 2-5), including industry-first PCIe 6 scale-up optics demonstrations leveraging COSMOS for end-to-end link management.
お知らせ • Apr 26Astera Labs, Inc., Annual General Meeting, Jun 04, 2026Astera Labs, Inc., Annual General Meeting, Jun 04, 2026. Location: offices of, astera labs, inc., at 2345 north first street, san jose, california 95131., san jose. United States
お知らせ • Apr 09Ultra Accelerator Link Consortium Publishes Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G PerformanceUltra Accelerator Link Consortium, the industry standards organization developing the open scale-up interconnect for next-generation AI workloads, announced the ratification of the next UALink Specification, which encompasses three major additions – In-Network Compute, Chiplet Definition, and Manageability. The new specifications support the deployment of UALink solutions in multi-workload environments, while simultaneously helping improve UALink technology efficiency, performance for AI workloads and ease of implementation. The UALink Consortium provides a standardized foundation for accelerator connectivity at scale, helping drive innovation, increase deployment flexibility and support the rapidly growing performance demands of next-generation AI workloads. The new specification update is facilitated through UALink Consortium’s open governance model, which fosters innovation while enabling a robust, multi-vendor supply chain, providing system designers and cloud providers with the necessary flexibility to deploy interoperable solutions without vendor lock-in. New UALink Specifications: UALink Common Specification 2.0 introduces In-Network Compute for UALink technology, facilitating computation and communication between accelerators. Reduces latency, saves bandwidth, and improves scaling efficiency for distributed training and inference for AI solutions for complex and multi-workload environments for UALink systems. UALink 200G Data Link and Physical Layers (DL/PL) Specification 2.0 split the DL/PL Specification from the UALink Common Specification to enable UALink to move quickly as new physical layers and speeds are needed by the industry without requiring changes to the other specifications. UALink Manageability Specification 1.0 introduces UALink as a system with centralized control and management planes. Utilizes standardized protocols, modeling and APIs like gNMI, Yang, SAI and Redfish. UALink Chiplet Specification 1.0 defines the necessary information to integrate UALink technology into chiplet-based SoCs, including interfaces, form factors, flow control and chiplet management standardization. Fully compliant with the UCIe 3.0 Specification for simplified integration into existing chiplet ecosystems. All of the UALink specifications are available for public download.
お知らせ • Apr 03Astera Labs, Inc. to Report Q1, 2026 Results on May 05, 2026Astera Labs, Inc. announced that they will report Q1, 2026 results After-Market on May 05, 2026
お知らせ • Feb 11+ 1 more updateAstera Labs, Inc. Announces Chief Financial Officer Changes, Effective March 2, 2026Astera Labs, Inc. appointed Desmond Lynch, age 46, as Chief Financial Officer, effective March 2, 2026. Desmond Lynch previously served as Senior Vice President, Finance and Chief Financial Officer of Rambus Inc. from August 2022 until February 2026 and served as the Vice President of Finance and Investor Relations of Rambus from 2020 until 2022. In addition, Desmond Lynch served as Vice President, Finance of Knowles Corporation, an audio solutions company, from 2019 to 2020. Previously, Desmond Lynch served as Vice President, Finance/Senior Director, Financial Planning and Analysis at Renesas Electronics Corporation/Integrated Device Technology, Inc., an analog and mixed signal semiconductor company, from 2016 to 2019. Desmond Lynch also served as Director, Financial Planning and Analysis at Atmel Corporation, a semiconductor company, from 2010 to 2016, prior to its acquisition by Microchip Technology. Desmond Lynch received a bachelor's degree in Accounting and Finance from the University of Glasgow, Scotland, in 2000, and is a Chartered Accountant with the Institute of Chartered Accountants of Scotland. On February 4, 2026, Michael Tate notified the Company of his retirement as Chief Financial Officer of the Company, effective March 2, 2026. Mr. Tate remains an employee of the Company and will transition to a role as Strategic Advisor to the CEO until September 1, 2026.
